• 전력전자학회논문지
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• 제12권6호
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• pp.500-509
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• 2007

본 논문에서는 FPGA를 사용하여 진행파형 초음파모터의 2상 입력 전원 전압의 주파수, 전압, 전압차 및 2상 간의 위상차 조절이 가능하고, 최대 8대의 초음파모터를 동시에 제어할 수 있는 PC기반 8채널 USB통신 초음파모터 디지털 제어기를 제안한다. 제안한 제어기는 FPGA를 사용한 디지털 논리에 의해 각각의 파라미터를 실시간으로 조절할 수 있을 뿐만 아니라 속도 및 위치 센서인 로터리 엔코더의 카운터 회로를 FPGA 회로에 내장시킴으로써 별도의 외부 회로 구성이 불필요하여 제어기의 크기나 생산비용의 절감을 기대할 수 있다. 제안한 새로운 방식의 제어기의 성능을 검사하기 위해서 홀딩토크가 다른 2가지 타입의 초음파모터에 대한 각 파라미터 조절에 따른 무부하 속도 특성을 실험하였다.

• Journal of Power Electronics
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• 제12권6호
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• pp.974-981
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• 2012

A FPGA based delta modulated single phase matrix converter has been developed that may be used in both cyclo-converters and cyclo-inverters. This converter is ideal for variable speed electrical drives, induction heating, fluorescent lighting, ballasts and high frequency power supplies. The peripheral input-output and FPGA interfacing have been developed through Xilinx 9.2i, to generate delta modulated trigger pulses for the converter. The controller has been relieved of the time consuming computational task of PWM signal generation by implementing the method of trigger pulse generation in a FPGA by using Hardware Description Language VHDL in Xilinx. The trigger circuit has been tested qualitatively by observing various waveforms on an oscilloscope. The operation of the proposed system has been found to be satisfactory.

• 융합신호처리학회논문지
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• 제11권1호
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• pp.53-62
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• 2010

최근 전자제어 차량을 비롯한 각종 산업용 임베디드 시스템은 분산형 다중 마이크로 컨트롤러 시스템으로 진화하고 있다. 이에 따라 제어의 효율성이 큰 객체지향형 시스템 구축이 용이하고, 통신의 높은 안정성과 신뢰성이 보장되는 표준적 CAN(Contro11er Area Network) 통신 규약이 필요하게 되었다. 기존의 범용 프로세서를 이용한 CAN 통신 인터페이스는 하드웨어 아키텍처가 고정되어 있기 때문에 다양한 응용에 적용함에 있어 유연성이 결여되는 등의 많은 한계를 가진다. 본 논문에서는 FPGA 기반 CAN 통신 인터페이스 시스템을 설계 구현하고, 기존의 AT90CAN128 컨트롤러와의 통신 성능을 모니터링 하여 시스템의 기능과 성능을 검증하였다. 본 연구의 CAN 인터페이스 시스템은 IFI_Nios_II_Advanced CAN IP 코어와 NIOS II 소프트 코어 프로세서를 사용하여 설계 되었다. 이에 따라 개발된 CAN 통신 인터페이스는 다양한 FPGA 기반 응용 시스템 개발에 재사용 릴 수 있고, 저비용, 소형화 그리고 저전력화를 달성할 수 있다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.1012-1015
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• 2003

Recently technologies have created new principle and theory but the PID control system remains its popularity as the PID controller contains simple structure, including maintenance and parameter adjustment being so simple. The adjust parameter of PID to achieve best response of process which be using time and may be error if user are not expert. Nowadays this problem was solved by develop PID controller which can analysis and auto tune parameter are appropriate with process which used principle of Ziegler ? Nichols but it are expensive and designed for each task. Thus, this paper proposes auto tune PID based on FPGA by use principle of Dahlin which maximum overshoot not over 5 percentages and do not fine tuning again. It have performance in control process are neighboring controller in industrial and simple to use. Especially, It can use various process and low price. The auto tune digital PID processor embedded on chip FPGA XC2S50-5tq-144. The digital PID processor was designed by fundamental PID equation which architectures including multiplier, adder, subtracter and some other logic gate. It was verified by control model of temperature control system.

• 제어로봇시스템학회논문지
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• 제22권8호
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• pp.671-677
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• 2016

A Controller Area Network (CAN) is a serial communication protocol that is highly reliable and efficient in many aspects, such as wiring cost and space, system flexibility, and network maintenance. Therefore, it is chosen for the communication protocol between a single chip controller based on Field Programmable Gate Array (FPGA) and peripheral devices. In this paper, the design and implementation of CAN IP, which is written in VHSIC Hardware Description Language (VHDL), is presented. The implemented CAN IP is based on the CAN 2.0A specification. The CAN IP consists of three processes: clock generator, bit timing, and bit streaming. The clock generator process generates a time quantum clock. The bit timing process does synchronization, receives bits from the Rx port, and transmits bits to the Tx port. The bit streaming process generates a bit stream, which is made from a message received from a micro controller subsystem, receives a bit stream from the bit timing process, and handles errors depending on the state of the CAN node and CAN message fields. The implemented CAN IP is synthesized and downloaded into SmartFusion FPGA. Simulations using ModelSim and chip test results show that the implemented CAN IP conforms to the CAN 2.0A specification.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2011년도 제42회 하계학술대회
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• pp.1306-1307
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• 2011

Recently, the small scale photovoltaic (PV) electronic devices are drawing attention as the upcoming PV generation system. The PV system is commonly used in small scale PV applications such as LED lighting and cell phone. This paper proposes photovoltaic output sensorless (POS) maximum power point tracking (MPPT) control for a small scale charging system of PV-nickel metal hydride battery using field-programmable gate array (FPGA) controller. A converter is connected to a small scale PV cell and battery, and performs the POS MPPT at the battery terminal current instead of being at the PV cell output voltage and current. The FPGA controller and converter operate based on POS MPPT method. The experimental results show that the nickel metal hydride battery is charged by the maximum PV output power.

• 전기학회논문지
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• 제61권1호
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• pp.80-84
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• 2012

Recently, the small scale photovoltaic (PV) electronic devices are drawing attention as the upcoming PV generation system. The PV system is commonly used in small scale PV applications such as LED lighting and cell phone. This paper proposes photovoltaic output sensorless (POS) maximum power point tracking (MPPT) control for a small scale charging system of PV-nickel metal hydride battery using field-programmable gate array (FPGA) controller. A converter is connected to a small scale PV cell and battery, and performs the POS MPPT at the battery terminal current instead of being at the PV cell output voltage and current. The FPGA controller and converter operate based on POS MPPT method. The experimental results show that the nickel metal hydride battery is charged by the maximum PV output power.

• Journal of Power Electronics
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• 제9권3호
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• pp.507-515
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• 2009

This paper proposes an autonomous decentralized control for a parallel connected uninterruptible power supply (UPS) system based on a fast power detection method using a FPGA based hardware controller for a single phase system. Each UPS unit detects only its output voltage and current without communications signal exchange and a quasi dq transformation method is applied to detect the phase and amplitude of the output voltage and the output current for the single phase system. Fast power detection can be achieved based on a quasi dq transformation, which results in a realization of very fast transient response under rapid load change. In the proposed method, the entire control system is implemented in one FPGA chip. Complicated calculations are assigned to hardware calculation logic, and the parallel processing circuit makes it possible to realize minimized calculation time. Also, an Nios II CPU core is implemented in the same FPGA chip, and the software can be applied for non-time critical calculations. Applying this control system, an autonomous decentralized UPS system with very fast transient response is realized. Feasibility and stable operation are confirmed by means of an experimental setup with three UPSs connected in parallel. Also, rapid load change is applied and excellent performance of the system is confirmed in terms of transient response and stability.

• 한국정보과학회:학술대회논문집
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• 한국정보과학회 2008년도 한국컴퓨터종합학술대회논문집 Vol.35 No.1 (D)
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• pp.327-331
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• 2008

본 논문에서는 ALtera Cyclone II FPGA와 VGA Controller, ISP1362 Host Controller, DM9000A Ethernet Controller를 사용하여 FPGA를 구성하고, ${\mu}Clinux$를 포팅하여 Nano-X 기반에서 JPEG 파일을 디스플레이 시키는 임베디드 디지털 액자를 구현한다. 구현한 시스템은 일반적인 마이크로프로세서를 사용하지 않고 Altera 사의 Cyclone II FPGA를 이용해 직접 프로세서를 설계하고, ISP1362 Host Controller를 이용하여 USB 드라이브를 인식하며, DM9000A를 통해 웹과 연결하여 웹서버로부터 전송되어진 JPEG 이미지를 Display 할 수 있도록 설계하였다.

• 제어로봇시스템학회논문지
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• 제13권12호
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• pp.1153-1159
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• 2007

This paper presents the hardware implementation of nonlinear PID controllers for the ROBOKER humanoid robot arms. To design the nonlinear PID controller on an FPGA chip, nonlinear functions as well as the conventional PID control algorithm have to be implemented by the hardware description language. Therefore, nonlinear functions such as trigonometric or exponential functions are designed on an FPGA chip. Simulation studies of the position control of humanoid arms are conducted and results are compared. Superior performances by the nonlinear PID controllers are confirmed when disturbances are present. Experiments of humanoid robot arm control tasks are conducted to confirm the performance of our hardware design and the simulation results.