• Journal of KIISE:Computing Practices and Letters
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• v.15 no.11
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• pp.801-805
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• 2009

Hardware based dynamic voltage and frequency scaling is a promising technique to reduce power consumption in a globally asynchronous locally synchronous system such as a homogeneous or heterogeneous multi-core system. In this paper, FPGA prototype design of hardware based dynamic frequency scaling is proposed. The proposed techniques are applied to a FIFO based multi-core system for a software defined radio and Network-on-Chip based hardware MPEG2 encoder. Compared with a references system using a single global clock, the first prototype design reduces the power consumption by 78%, but decreases the performance by 5.9%. The second prototype design shows that power consumption decreases by 29.1% while performance decreases by 0.36%.

• Journal of Communications and Networks
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• v.1 no.3
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• pp.201-212
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• 1999

This paper studies the rapid design and implementation of the medium access control(MAC) and related interface circuits for 802.11 wireless LANs based on the field programmed gate ar-ray(FPGA) technology. Our design is thus aimed to support both the distributed coordination function (DCF) and the point coordination function(PCF) with the aid of FPGA technology. Further-more, in an infrastructure network, some stations may serve as the access points (APs) which may function like a learning bridge. This paper will also discuss how to design for such application. The hardware of the MAC and interface may at least consist of three major parts: wireless transmission and reception processes and in-terface, host(bus) interface, and the interface to the distributed system (optional). Through the increasing popularity of FPGA de-sign, this paper presents how Complex Programmable Logic De-vices(CPLD) can be utilized for speedy design of prototypes. It also demonstrates that there is much room for low-cost hardware prototype design to accelerate the processing speed of the MAC control function and for field testing.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.9 no.6
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• pp.2201-2216
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• 2015

Peak to average power ratio (PAPR) is one of the main imperfections in the broadband communication systems with multiple carriers. In this paper, a new crest factor reduction (CFR) scheme based on interleaved phase sequence called Dummy Sequence Insertion Enhanced Partial Transmit Sequence (DSI-EPTS) is proposed which effectively reduces the PAPR while at the same time keeps the total complexity low. Moreover, the prototype of the proposed scheme in field programmable gate array (FPGA) is demonstrated. In DSI-EPTS scheme, a new matrix of phase sequence is defined which leads to a significant reduction in hardware complexity due to its less searching operation to extract the optimum phase sequence. The obtained results show comparable performance with slight difference due to the FPGA constraints. The results show 5 dB reduction in PAPR by applying the DSI-EPTS scheme with low complexity and low power consumption.

• Proceedings of the Korea Information Processing Society Conference
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• 2007.05a
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• pp.1117-1120
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• 2007

본 논문에서는 개선된 F함수를 이용 하여 국내 표준 128비트 블록 암호화 알고리듬인 SEED 암호 프로세서의 FPGA 구현에 관하여 기술한다. 제안한 SEED 암호 프로세서는 Verilog-HDL를 사용하여 구조적 모델링을 하였으며, Xilinx사의 ISE 9.1i 툴을 이용하여 논리 합성을 수행하였다. 설계 검증은 Modelsim 6.2c 툴을 이용하여 타이밍 시뮬레이션을 수행하였으며, FPGA Prototype 시스템을 사용하여 설계된 하드웨어 동작을 검증하였다.

• Proceedings of the KIEE Conference
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• 2001.11c
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• pp.209-211
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• 2001

The core in developing the transformer-operated 3 phase solid state meter is to design a single chip IC, that incorporates all the necessary features required for development of the 3 phase solid state meter. Using this technology, the solid state meter can be mass produced at lower cost and higher quality. This report deals with the performance of the prototype FPGA board, which is the final step before actual IC fabrication in fabrication LAB. All the features of FPGA board, shown in this report will be included in the final ASIC IC product.

• Journal of Electrical Engineering and Technology
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• v.10 no.4
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• pp.1655-1666
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• 2015

This paper proposes a new approach of Field Programmable Gate Array (FPGA) controlled digital implementation of shunt active power filter (SAPF) under steady state and dynamic operations. Typical implementations of SAPF uses microprocessor and digital signal processor (DSP) but it limited for complex algorithm structure, absence of feedback loop delays and their cost can be exceed the benefit they bring. In this paper, the hardware resources of an FPGA are configured and implemented in order to overcome conventional microcontroller or digital signal processor implementations. This proposed FPGA digital implementation scheme has very less execution time and boosts the overall performance of the system. The FPGA controller integrates the entire control algorithm of an SAPF, including synchronous reference frame transformation, phase locked loop, low pass filter and inverter current controller etc. All these required algorithms are implemented with a single all-on chip FPGA module which provides freedom to reconfigure for any other applications. The entire algorithm is coded, processed and simulated using Xilinx 12.1 ISE suite to estimate the advantages of the proposed system. The coded algorithm is also defused on a single all-on-chip Xilinx Spartan 3A DSP-XC3SD1800 laboratory prototype and experimental results thus obtained match with simulated counterparts under the dynamic state and steady state operating conditions.

• Nuclear Engineering and Technology
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• v.45 no.4
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• pp.477-488
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• 2013

The PLC (Programmable Logic Controller) has been widely used to implement real-time controllers in nuclear RPSs (Reactor Protection Systems). Increasing complexity and maintenance cost, however, are now demanding more powerful and cost-effective implementation such as FPGA (Field-Programmable Gate Array). Abandoning all experience and knowledge accumulated over the decades and starting an all-new development approach is too risky for such safety-critical systems. This paper proposes an RPS software development process with a platform change from PLC to FPGA, while retaining all outputs from the established development. This paper transforms FBD designs of the PLC-based software development into a behaviorally-equivalent Verilog program, which is a starting point of a typical FPGA-based hardware development. We expect that the proposed software development process can bridge the gap between two software developing approaches with different platforms, such as PLC and FPGA. This paper also demonstrates its effectiveness using an example of a prototype version of a real-world RPS in Korea.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.4
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• pp.15-25
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• 2012

The research on the FPGA CAD tools in academia has been lacking practicality due to the underlying FPGA fabric architecture which is too simple and inefficient to be applied for commercial FPGAs. Recently, the database of placement positions and routing graphs on commercial FPGA architectures has been built, and provided for enabling the academic development of placement and routing tools. To extend the limit of academic CAD tools even further, we have developed the evaluation toolkit for the K-FPGA architecture which is under development. By providing interface for exchanging data with a commercial FPGA toolkit at every step of mapping, packing, placement and routing in the tool chain, the toolkit enables individual tools to be developed without waiting for the results of the preceding step, and with no dependency on the quality of the results, and compared in detail with commercial tools at any step. Also, the fabric primitive library is developed by extracting the prototype from a reporting file of a commercial FPGA, restructuring it, and modeling the behavior of basic gates. This library can be used as the benchmarking target, and a reference design for new FPGA architectures. Since the architecture is described in a standard HDL which is familiar with hardware designers, and read in the tools rather than hard coded, the tools are "data-driven", and tolerable with the architectural changes due to the design space exploration. The experiments confirm that the developed library is correct, and the functional correctness of applications implemented on the FPGA fabric can be validated by simulation. The placement and routing tools are under development. The completion of the toolkit will enable the development of practical FPGA architectures which, in return, will synergically animate the research on optimization CAD tools.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.5
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• pp.257-266
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• 2006

Recently TCP/IP Offload Engine (TOE) technology, which processes TCP/IP on a network adapter instead of the host CPU, has become an important approach to reduce TCP/IP processing overhead in the host CPU. There have been two approaches to implementing TOE: software TOE, in which TCP/IP is processed by an embedded processor on a network adapter; and hardware TOE, in which all TCP/IP functions are implemented by hardware. This paper proposes a hybrid TOE that combines software and hardware functions in the TOE. In the hybrid TOE, functions that cannot have guaranteed performance on an embedded processor because of heavy load are implemented by hardware. Other functions that do not impose as much load are implemented by software on embedded processors. The hybrid TOE guarantees network performance near that of hardware TOE and it has the advantage of flexibility, because it is easy to add new functions or offload upper-level protocols of TCP/IP. In this paper, we developed a prototype board with an FPGA and an ARM processor to implement a hybrid TOE prototype. We implemented the hardware modules on the FPGA and the software modules on the ARM processor. We also developed a coprocessing mechanism between the hardware and software modules. Experimental results proved that the hybrid TOE prototype can greatly reduce the load on a host CPU and we analyzed the effects of the coprocessing mechanism. Finally, we analyzed important features that are required to implement a complete hybrid TOE and we predict its performance.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.670-673
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• 2008

Optimized algorithms and numerical expressions which had been verified through C program simulation, should be analyzed again with HDL (hardware description language) such as Verilog, so that the verified ones could be modified to be applied directly to hardware implementation. The reason is that the characteristics of C programming language design is intrinsically different from the hardware design structure. The hardware IP verified doubly in view of hardware structure together with algorithmic verification, was implemented on the Altera Excalibur FPGA device equipped with ARM9 microprocessor core, to a real chip prototype, using Altera embedded system development tool kit. The implemented finite field calculation IPs can be used as library modules as Elliptic Curve Cryptography finite field operations which has more than 193 bit key length.