• 한국컴퓨터산업교육학회:학술대회논문집
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• 2003.11a
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• pp.5-10
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• 2003

본 논문에서는 wavelet을 이용한 워터마크 삽입 시스템 구현을 제안한다. wavelet 변환 기법은 JPEG2000 이나 MPEG-4와 같은 차세대 데이터 압축 표준의 기본적 연산으로서 DCT연산에 비해 주파수 해상도와 시간해상도를 모두 만족시킨다. 제안한 시스템은 크게 DWT 변환모듈, 워터마크 삽입모듈, IDWT 복원모듈, Main Controller모듈로 구성된다. DWT 변환모듈은 Haar 웨이블렛 변환알고리즘을 기반으로 설계 됐으며 1차 신축을 통해 변환된 주파수 영역에서 중간주파수 대역(LH 및 HL)을 선택하여 워터마크를 삽입하는 워터마크 삽입 모듈, IDWT를 이용 신호를 복원하는 모듈, 전체시스템 구성 블록을 제어하는 Main Controller모듈로 구성된다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.10C
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• pp.999-1007
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• 2002

In this paper, the operation of matched filter for searching initial synchronization in direct sequence spread spectrum receiver is studied. The implementation model of the matched filter by HDL (Hardware Description Language) is proposed. The model has an architecture based on parallelism and pipeline for fast processing, which includes circular buffer, multiplier, adder, and code look-up table. The performance of the model is analyzed and compared with the implementation by a conventional digital signal processor. It is implemented on a FPGA (Field Programmable Gate Array) and its operation is validated in a timing simulation result.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.2 no.1
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• pp.147-156
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• 1998

In this paper, an arithmetic processor using multi-valued logic is designed. For implementing of multi-valued logic circuits, we use current-mode CMOS circuits and design encoder which change binary voltage-mode signals to multi-valued current-mode signals and decoder which change results of arithmetic to binary voltage-mode signals. To reduce the number of partial product we use 4-radix SD number partial product generation algorithm that is an extension of the modified Booth's algorithm. We demonstrate the effectiveness of the proposed arithmetic circuits through SPICE simulation and Hardware emulation using FPGA chip.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.890-893
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• 2014

In this paper, we present a signal processing algorithm for a marine radar system, in which the evaluation of probability of collision as well as target detection and tracking are performed. Moreover, the digital signal processor that implements the algorithm is proposed. As simulation environment, a mechanically scanning antenna utilizing FMCW signal is used, conducting the beamforming operation with 1 degrees intervals. Test board consists of DSP chips and FPGA, which enable the implemented system to operate in real-time.

• The KIPS Transactions:PartA
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• v.14A no.7
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• pp.391-398
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• 2007

In this paper, we design a future mobile camera standard interface based on the MIPI CSI-2 and D-PHY specification. The proposed CSI-2 have the efficient multi-lane management layer, which the independent buffer on the each lane are merged into single buffer. This scheme can flexibly manage data on multi lanes though the number of supported lanes are mismatched in a camera processor transmitter and a host processor. The proposed CSI-2 & D-PHY are verified under test bench. We make an experiment on CSI-2 & D-PHY with FPGA type test-bed and implement them onto a mobile handset. The proposed CSI-2 & D-PHY module are used as both the bridge type and the future camera processor IP for SoC.

• 전자공학회논문지 IE
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• v.48 no.3
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• pp.20-25
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• 2011

We developed a method of accelerating the operation speed of communication systems for SDR(Software Defined Radio) systems in WiBro environment. In this paper, we propose a new scheme of using GPU(Graphics Processing Unit) for implementing the communication system which perform with the functionality of SDR. In general, communication systems is made by DSP(Digital Signalling Processor) or FPGA(Field Programmable Gate Array). However, in this case, there are exist the problem of implementation and debugging caused by each CPU characteristic. The GPU is optimized for vector processing because it usually consists of multiple processors and each processor in GPU is composed of a set of threads. We also developed Framework to use GPU and CPU resources effectively for reducing the operation time. From the various simulation, it is confirmed that GPU system have good performance in WiBro system.

• Journal of Institute of Control, Robotics and Systems
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• v.8 no.12
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• pp.1036-1040
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• 2002

To process data of digital linescan camera, the frame grabber is essential to handle the data in low-level and in high speed more than 30 MHz stably. Traditional approaches to the development of hardware in vision system for the special purpose are mai y based on PC system, and are expensive and gigantic. Therefore, there are many difficulties in applying those in the field. So we investigate, in this paper, the implementation of FPGA for real-time processing of digital linescan camera. The system is not based on PC, but electronic device such as micropncessor. So it is expected that the use of FPGAs for low-level processing represents a fast, stable and inexpensive system. The experiments are carried out on the web guiding system in order to show the efficiency of the new image processor.

• Journal of Institute of Control, Robotics and Systems
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• v.15 no.11
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• pp.1137-1143
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• 2009

This paper presents the FPGA implementation of efficient algorithms for approximating exponential function based on floating point format data. The Taylor-Maclaurin expansion as a conventional approximation method becomes inefficient since high order expansion is required for the large number to satisfy the approximation error. A format converter is designed to convert fixed data format to floating data format, and then the real number is separated into two fields, an integer field and an exponent field to separately perform mathematic operations. A new assembly command is designed and added to previously developed command set to refer the math table. To test the proposed algorithm, assembly program has been developed. The program is downloaded into the Altera DSP KIT W/STRATIX II EP2S180N Board. Performances of the proposed method are compared with those of the Taylor-Maclaurin expansion.

• Proceedings of the Korea Information Processing Society Conference
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• 2007.05a
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• pp.1117-1120
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• 2007

본 논문에서는 개선된 F함수를 이용 하여 국내 표준 128비트 블록 암호화 알고리듬인 SEED 암호 프로세서의 FPGA 구현에 관하여 기술한다. 제안한 SEED 암호 프로세서는 Verilog-HDL를 사용하여 구조적 모델링을 하였으며, Xilinx사의 ISE 9.1i 툴을 이용하여 논리 합성을 수행하였다. 설계 검증은 Modelsim 6.2c 툴을 이용하여 타이밍 시뮬레이션을 수행하였으며, FPGA Prototype 시스템을 사용하여 설계된 하드웨어 동작을 검증하였다.

• Proceedings of the KIEE Conference
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• 2002.07d
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• pp.2628-2630
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• 2002

This paper describes the design and implementation of the OFDM Modem using FPGA. The proposed OFDM method is based on IEEE 802.11a high-speed wireless LAN standard. The proposed and designed Pipeline FFT processor adopt the Radix-$2^2$SDF scheme. This method has a simple architecture and highly increases the calculation speed. And also it decreases the required number of registers. Therefore the proposed OFDM Modem reduces hardware size and improves the calculation speed. The OFDM Modem is implemented using $FLEX^{TM}$ FPGA.