• Proceedings of the KIEE Conference
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• 2001.07b
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• pp.1212-1214
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• 2001

In this paper ASIC design technique using VHDL is applied to MRAS based speed sensorless control of induction motor. ASIC for MRAS based speed sensorless control is designed through the description of speed estimator using FSM, stator voltage controller, flux angle detector, coordinate transformation, and inverter switching signal output. Finally the above system has been implemented on the FPGA (VERTEX XCV400HQ240). Simulation and experiment have been performed to verify the performance of the designed ASIC.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.52 no.1
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• pp.20-27
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• 2003

In this study, we designed and made Ultrasonic motor-digital multi controller(USM-DMC) using FPGA chip, A54SX72A made in Actel Corporation. By the minute, USM-DMC can adjust the frequency, duty ratio, and phase difference parameters of USM by digital input to be each 11bit from PC. Therefore, when we use this controller, it is possible to apply typical three parameters individually as well as multi-parameters simultaneously to control the speed and the torque. What is more, the strongest point is that it can trace frequency based on optimized frequency as compared with the phase difference because we can input optimized resonant frequency while in motoring. And we test the speed of USM with the adjustment of multi-parameters, the phase difference-frequency. As the result of the test, in the case of the multi-parameters of the phase difference and frequency, the speed characteristic is more linear and stable, and wider in the range of control than the single-parameter of the phase difference or the frequency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.3
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• pp.558-567
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• 2003

Most digital signal processors provide 4 external interrupt input channels. But these are not sufficient for external interrupts of motor controls. Customized programmable interrupt controller, 8259, has 8 interrupt channels. Therefore, in the case of more external interrupt channels are needed, designers must expand by cascading the 8259. And this, 8259 device, have some inconvenience of interfacing the microprocessor in motor controls. In this paper, the expanded interrupt controller with 14 sufficient interrupt input channels for motor controls is designed using VHDL on the purpose of interfacing the microprocessor to the interrupt controller more compatibly and increasing the device utilization of FPGA/CPLD designed another peripherals. The interrupt controller model and each function blocks is proposed and illustrated. Simulation result are presented to estimate the designed interrupt controller.

• Journal of Power Electronics
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• v.16 no.1
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• pp.190-204
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• 2016

An active front end (AFE) is required for a three-phase induction motor (IM) fed by a voltage source inverter (VSI), because of the increasing need to derive quality current from the utility end without sacrificing the power factor (PF). This study investigates a proportional-plus-integral (PI) controller based AFE topology that uses a super-lift converter (SLC). The significance of the proposed SLC, which converts rectified AC supply to geometrically proceed ripple-free DC supply, is explained. Variations in several power quality parameters in the intended IM drive for 0% and 100% loading conditions are demonstrated. A simulation is conducted by using MATLAB/Simulink software, and a prototype is built with a field programmable gate array (FPGA) Spartan-6 processor. Simulation results are correlated with the experimental results obtained from a 0.5 HP IM drive prototype with speed feedback and a voltage/frequency (V/f) control strategy. The proposed AFE topology using SLC is suitable for three-phase IM drives, considering the supply end PF, the DC-link voltage and current, the total harmonic distortion (THD) in supply current, and the speed response of IM.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.11
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• pp.1564-1570
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• 2015

This paper intends to suggest a sensing circuit of PWM voltage for a motor emulator operated in the inverter. In the emulation of the motor using a power converter, it is necessary to measure instantaneous voltage at the PWM voltage loaded from the inverter. Using a filter can generate instantaneous voltage, while it is difficult to follow the rapidly changing inverter voltage caused by the propagation delay and signal attenuation. The method of measuring the duty of PWM using FPGA can generate output voltage from the one-cycle delay of PWM, while the cost of hardware is increasing in order to acquire high precision. This paper suggests a PWM voltage sensing circuit using the analogue system that shows high precision, one-cycle delay of PWM and low-cost hardware. The PWM voltage sensing circuit works in the process of integrating input voltage for valid time by comparing levels of three-phase PWM input voltage, and produce the output value integrated at zero vector. As a result of PSIM simulation and the experiment with the produced hardware, it was verified that the suggested circuit in this paper is valid.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1022-1027
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• 2003

The Motion controllers provide the sophisticated performance and enhanced capabilities we can see in the movements of robotic systems. Several types of motion controllers are available, some based on the kind of overall control system in use. PLC (Programmable Logic Controller)-based motion controllers still predominate. The many peoples use MCU (Micro Controller Unit)-based board level motion controllers and will continue to in the near-term future. These motion controllers control a variety motor system like robotic systems. Generally, They consist of large and complex circuits. PLC-based motion controller consists of high performance PLC, development tool, and application specific software. It can be cause to generate several problems that are large size and space, much cabling, and additional high coasts. MCU-based motion controller consists of memories like ROM and RAM, I/O interface ports, and decoder in order to operate MCU. Additionally, it needs DPRAM to communicate with host PC, counter to get position information of motor by using encoder signal, additional circuits to control servo, and application specific software to generate a various velocity profiles. It can be causes to generate several problems that are overall system complexity, large size and space, much cabling, large power consumption and additional high costs. Also, it needs much times to calculate velocity profile because of generating by software method and don't generate various velocity profiles like arbitrary velocity profile. Therefore, It is hard to generate expected various velocity profiles. And further, to embed real-time OS (Operating System) is considered for more reliable motion control. In this paper, the structure of chip-based precision motion controller is proposed to solve above-mentioned problems of control systems. This proposed motion controller is designed with a FPGA (Field Programmable Gate Arrays) by using the VHDL (Very high speed integrated circuit Hardware Description Language) and Handel-C that is program language for deign hardware. This motion controller consists of Velocity Profile Generator (VPG) part to generate expected various velocity profiles, PCI Interface part to communicate with host PC, Feedback Counter part to get position information by using encoder signal, Clock Generator to generate expected various clock signal, Controller part to control position of motor with generated velocity profile and position information, and Data Converter part to convert and transmit compatible data to D/A converter.

• Journal of Power Electronics
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• v.11 no.4
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• pp.401-407
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• 2011

In order to enhance torque density of five-phase permanent magnetic synchronous motor with third harmonic injection for electric vehicles (EVs) applications, optimum seeking method for injection ratio of third harmonic was proposed adopting theoretical derivation and finite element analysis method, under the constraint of same amplitude for current and air-gap flux. By five-dimension space vector decomposition, the mathematic model in two orthogonal space plane, $d_1-q_1$ and $d_3-q_3$, was deduced. And the corresponding dual-plane vector control method was accomplished to independently control fundamental and third harmonic currents in each vector plane. A five-phase PMSM prototype with quasi-trapezoidal flux pattern and its fivephase voltage source inverter were designed. Also, the dual-plane vector control was digitized in a single XC3S1200E FPGA. Simulation and experimental results prove that using the proposed optimum seeking method, the torque density of five-phase PMSM is enhanced by 20%, without any increase of power converter capacity, machine size and iron core saturation.

• Journal of Advanced Navigation Technology
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• v.18 no.2
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• pp.142-150
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• 2014

In this paper, the performance analysis results of time/frequency synchronization and cell search algorithm are presented for aeronautical mobile airport communication systems (AeroMACS). AeroMACS is based on IEEE 802.16e mobile WiMAX standard and uses the aeronautical frequency band of 5GHz with the bandwidth of 5MHz. The simulation model of AeroMACS is designed and the performance evaluation is conducted with the various airport channel models such as apron (APR), runway (RWY), taxiway (TWY), and park (PRK). The proposed synchronization unit was designed in hardware description language (HDL) and implemented on FPGA. Also, the real-time operation was verified and evaluated using FPGA test system.

• Journal of IKEEE
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• v.26 no.1
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• pp.43-49
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• 2022

This paper compares the sensorless control performance according to the applied voltage waveform by injecting sinusoidal, triangular, and square waveform in the harmonic injection sensorless control method. By injecting various voltage shape waveform with a frequency of 1kHz, the error amount of the estimated angle for each waveform is compared and analyzed. For the experiment, the HILS(hardware in the loop simulation) system was used. The hardware is the control board, and the inverter and motor models implemented in Simulik are located in the real-time simulator. The control algorithm is implemented by the FPGA control board, which includes a PWM interrupt service routine with a frequency of 10 kHz, harmonic injection and position detection sensorless algorithm.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.981-985
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• 2004

In this paper we designed the motor control IP Core and evaluate its quality from the viewpoint of IP reuse. The most attractive merit of this methodology, so called IP-based hardware design, is hardware reuse. Although various vendors designed hardware with the same specification and got the same functional results, all that IPs is not the same quality in the reuse aspect. As tremendous calls for SoC have been increased, associated research about IP quality standard, VSIA(Virtual Socket Interface Alliance) and STARC(Semiconductor Technology Academic Research Center), has been doing best to make the IP quality evaluation system. And they made what conforms to objective IP design standard. We suggest the methodology to evaluate our own designed motor control IP quality with this standard. To attain our goal, we designed motor control IP that could control the motor velocity and position with feedback compensation algorithm. This controller has some IP blocks : digital filter, quadrature decoder, position counter, motion compensator, and PWM generator. Each block's functionality was verified by simulator ModelSim and then its quality was evaluated. To evaluate the core, We use Vnavigator for lint test and ModelSim for coverage check. During lint process, We adapted the OpenMORE's rule based on RMM (Reuse Methodology Manual) and it could tell us our IP's quality in a manner of the scored value form. If it is high, its quality is also high, and vice versa. During coverage check ModelSim-SE is used for verifying how our test circuits cover designs. This objective methods using well-defined commercial coverage metrics could perform a quantitative analysis of simulation completeness. In this manner, We evaluated the designed motor control IP's quality from the viewpoint of reuse. This methodology will save the time and cost in designing SoC that should integrate various IPs. In addition to this, It can be the guide for comparing the equally specified IP's quality. After all, we are continuously looking forward to enhancing our motor control IP in the aspect of not only functional perfection but also IP reuse to prepare for the SoC-Compliant motor control IP design.