• Journal of Institute of Control, Robotics and Systems
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• v.13 no.7
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• pp.649-655
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• 2007

In this paper, a time-delayed controller for position control of humanoid robot arms is designed and implemented on a field programmable gate array(FPGA) chip. The time-delayed control algorithm is simple to implement, and robust to reject disturbances. The time-delayed control method uses the one sample time-delayed previous information to cancel out uncertainties in the system. Since the sampling time is so fast with the current hardware technology, the time-delayed controller can be implemented. However, inertia values should be correctly estimated to have the better performance. The position tracking tasks of humanoid robot arms are tested to compare performances of several control algorithms including the time-delayed controller.

• Journal of Institute of Control, Robotics and Systems
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• v.13 no.1
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• pp.33-38
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• 2007

In this paper, hardware implementation of interface and control between two robots, the master and the slave robot, are designed. The master robot is the motion capturing device that captures motions of the human operator who wears it. The slave robot is the corresponding humanoid robot arms. Captured motions from the master robot are transferred to the slave robot to follow after the master. All hardware designs such as PID controllers, communications between the master robot, encoder counters, and PWM generators are embedded on a single FPGA chip. Experimental studies are conducted to demonstrate the performance of the FPGA controller design.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.61 no.1
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• pp.47-54
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• 2012

This paper presents implementation of SVPWM technique for three phase Voltage Source Inverter using FPGA. Software-based vector-control calculations much this drawback, in order to improve the hardware-vector-control tries. Without the need for additional software, vector control algorithm is designed to be modular SOPC, and DSP will reduce most of the operations. In this paper, the SVPWM that using HDL for the AC motor vector control algorithm level, and the dead time part and the speed control in order to controled a speed detector and designed in the form of modules. Then ALTERA corporation Cyclone III series EP3C16F484 can be verified by implemented.

• Journal of Korea Multimedia Society
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• v.20 no.11
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• pp.1803-1810
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• 2017

A large amount of processing time is required if the process of detecting the touch position on the touch screen and displaying it on the display panel is performed only by software. In this paper, we propose a method to output information touched on the screen using H/W method in order to improve the response speed delay. In the FPGA module designed for the HDMI signal output to the display module, the touch information is input to the serial data signal including touch coordinate information, point size, and color information. Then the module render the image using HDMI signal input to the module and the touch information. This method has a pipeline structure so it has effect of reducing the delay time that occurs in outputting the touch information compared with the conventional software processing method.

• Journal of Korea Society of Digital Industry and Information Management
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• v.9 no.1
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• pp.129-139
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• 2013

In this paper, we proposed a new hardware architecture for calculating digital holograms at high speed, and verified it with field programmable gate array (FPGA). First, we rearranged memory scheduling and algorithm of computer generated hologram (CGH), and then introduced pipeline technique into CGH process. Finally we proposed a high-performance CGH processor. The hardware was implemented for the target of FPGA, which calculates a unit region of holograms, and it was verified using a hardware environment of NI Inc. and a FPGA of Xilinx Inc. It can generate a hologram of $16{\times}16$ size, and it takes about 4 sec for generating a hologram of a $1,024{\times}1,024$ size, using 6K point sources.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.445-446
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• 2006

This paper is concerned with a substantial speed up of image processing methods and less power consumption on 2D images making use of modern FPGA (Field Programmable Gate Array) technology. We implemented 2D FFT and edge detection algorithms based on FPGA and examined processing time and power consumption compared with C/C++ and Alti-Vec technologies.

• Proceedings of the IEEK Conference
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• 2002.06a
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• pp.287-290
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• 2002

This paper rotates to tile FPGA that is reffered to as the UTOSPI. The design goal of the FPGA is to convert the UTOPIA-3 bus interface to the SPI-3 bus interface, so that the SAR chips on the ATM interface board can be interfaced to the packet processor through this FPGA. We Propose a new architecture that has two Dual Port RAMs and flow control signals. To buffer data, the UTOSPI has a Dual port RAM in the receive direction and the same size of that in the transmit direction. This design has been implemented, compiled, and tested using a Xilinx Virtex-I XCV-300E FPGA.

• The KIPS Transactions:PartC
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• v.8C no.3
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• pp.277-286
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• 2001

본 논문에서는 미국 국립표준기술연구소 차세대 표준 암호 알고리듬으로 선정한 Rijndael 암호 알고리듬과 안정성과 성능에서 인정을 받은 Twofish 암호 알고리듬을 ALTERA FPGA를 사용하여 하드웨어로 구현한다. 두가지 알고리듬에 대해 키스케쥴링과 인터페이스를 하드웨어에 포함시켜 구현한다. 알고리듬의 효율적인 동작을 위해 키스케쥴링을 포함하면서도 구현된 회로의 크기가 크게 증가하지 않으며, 데이터의 암호/복호화 처리 속도가 향상됨을 알 수 있다. 주어진 128-비트 대칭키에 대하여, 구현된 Rijndael 암호 알고리듬은 11개의 클럭 만에 키스케쥴링을 완료하며, 구현된 Twofish 암호 알고리듬은 21개의 클럭 만에 키스케쥴링을 완료한다. 128-비트 입력 데이터가 주어졌을 때, Rijndael의 경우, 10개의 클럭 만에 주어진 데이터의 암호/복호화를 수행하고, Twofish는 16개의 클럭 만에 암호/복호화를 수행한다. 또한, Rijndael은 336.8Mbps의 데이터 처리속도를 보이고, Twofish는 121.2Mbps의 성능을 보임을 알 수 있다.

• Proceedings of the KIEE Conference
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• 2003.07d
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• pp.2678-2680
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• 2003

본 논문에서는 sliding-DFT의 순환구현을 기반한 실시간 위상 측정 앨고리즘을 제시하였다. 종래의 순환형 SDFT 기반 위상 측정 기법은 단일 계수를 사용하기 때문에 계수 근사가 적용되는 하드웨어 구현시 심각한 오차 파급 특성을 나타낸다. 본 논문에서는 순환 구조이면서 회전 위상을 보정을 통해 N-point DFT의 N개의 모든 계수를 적용한 위상 측정 기법을 제시하였고, FPGA 등 하드웨어 구현에 있어서 계수의 유한 비트 근사에 따르는 성능 열화를 해석하였다. 제안한 위상측정 앨고리즘은 실시간 다채널 위상 측정이 가능하도록 FPGA에 구현하였고 동작을 확인하였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2011.11a
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• pp.322-325
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• 2011

스테레오 비전 시스템에서 전통적인 매칭 알고리즘으로 SAD(Sum of Absolute Differences), SSD(Sum of Squared Differences), NCC(Normalized Cross Correlation) 등 다양한 알고리즘이 존재한다. 그러나 하드웨어로 실시간 처리를 위한 시스템을 구현하기 위해서는 리소스가 한정 되어있다는 제약 때문에 많은 연구에서 SAD 혹은 RT(Rank Transform), CT(Census Transform)를 많이 사용하게 된다. FPGA 내부에는 BRAM(Block RAM)과 MAC(multiply-accumulator)인 DSP슬라이스가 이미 존재한다. 본 논문에서는 BRAM과 DSP로직을 활용해서 전통적인 매칭 알고리즘 중에서 연산기 사용이 가장 많은 NCC를 FPGA로 실시간 처리 가능한 하드웨어 구조를 제안한다.