• Convergence Security Journal
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• v.7 no.2
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• pp.17-25
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• 2007

In this paper, an algorithm that provisions proportional differentiation of packet delays is proposed with an objective for enhancing quality of service (QoS) in future packet networks. It features an adaptive scheme that adjusts the target delay every time slot to compensate the deviation from the target delay which is caused by the prediction error on the traffic to be arrived in the next time slot. It predicts the traffic to be arrived at the beginning of a time slot and measures the actual arrived traffic at the end of the time slot. The difference between them is utilized to the delay control operation for the next time slot to offset it. As it compensates the prediction error continuously, it shows superior adaptability to the bursty traffic as well as the exponential rate traffic. It is demonstrated through simulations that the algorithm meets the quantitative delay bounds and shows superiority to the traffic fluctuation in comparison with the conventional non-adaptive mechanism. The algorithm is implemented with VHDL on a Xilinx Spartan XC3S1500 FPGA and the performance is verified under the test board based on the XPC860P CPU.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.12
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• pp.2628-2635
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• 2010

This paper analyzes the detection probability of FMCW (Frequency Modulated Continuous Wave) radar based on Doppler frequency and analog-digital converter bit and designs and implements signal processing part of FMCW radar. For performance evaluation, the FMCW radar system consists of a transmitted part and a received part and uses AWGN channel. The system model is verified through analysis and simulation. Frequency offset occurs in the received part caused by the mismatching between the received signal and the reference signal. In case of Doppler frequency less than about 38KHz, performance degradation of detection does not occur in FMCW radar with 75cm resolution The analog-digital converter needs at least 6 bit in order not to degrade the detection probability. And, we design and implement digital signal processing part based on DDS chip of digital transmitted signal generator for FMCW radar.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.2A
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• pp.129-136
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• 2005

A multiplier generator, VPM_Gen (Variable-Precision Multiplier Generator), which generates Verilog-HDL models of multiplier cores with user-defined bit-width specification, is described. The bit-widths of operands are parameterized in the range of $8-bit{\sim}32-bit$ with 1-bit step, and the product from multiplier core can be truncated in the range of $8-bit{\sim}64-bit$ with 2-bit step, resulting that the VPM_Gen can generate 3,455 multiplier cores. In the case of truncating multiplier output, by eliminating the circuits corresponding to the truncation part, the gate counts and power dissipation can be reduced by about 40% and 30%, respectively, compared with full-precision multiplier. As a result, an area-efficient and low-power multiplier core can be obtained. To minimize truncation error, an adaptive error-compensation method considering the number of truncation bits is employed. The multiplier cores generated by VPM_Gen have been verified using Xilinx FFGA board and logic analyzer.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.8
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• pp.453-464
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• 2004

In order to solve the well-known drawback of reduced flexibility that is associate with ASIC implementations, this paper proposes a novel arithmetic unit over GF(2$^{m}$ ) for field programmable gate arrays (FPGAs) implementations of elliptic curve cryptographic processor. The proposed arithmetic unit is based on the binary extended GCD algorithm and the MSB-first multiplication scheme, and designed as systolic architecture to remove global signals broadcasting. The proposed architecture can perform both division and multiplication in GF(2$^{m}$ ). In other word, when input data come in continuously, it produces division results at a rate of one per m clock cycles after an initial delay of 5m-2 in division mode and multiplication results at a rate of one per m clock cycles after an initial delay of 3m in multiplication mode respectively. Analysis shows that while previously proposed dividers have area complexity of Ο(m$^2$) or Ο(mㆍ(log$_2$$^{m}$ )), the Proposed architecture has area complexity of Ο(m), In addition, the proposed architecture has significantly less computational delay time compared with the divider which has area complexity of Ο(mㆍ(log$_2$$^{m}$ )). FPGA implementation results of the proposed arithmetic unit, in which Altera's EP2A70F1508C-7 was used as the target device, show that it ran at maximum 121MHz and utilized 52% of the chip area in GF(2$^{571}$ ). Therefore, when elliptic curve cryptographic processor is implemented on FPGAs, the proposed arithmetic unit is well suited for both division and multiplication circuit.

• Journal of IKEEE
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• v.27 no.4
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• pp.624-629
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• 2023

Estimation of signal parameters via rotational invariance techniques (ESPRIT) is an algorithm that estimates the angle of a signal arriving at an array antenna using the shift invariance property of an array antenna. ESPRIT offers the good trade-off between performance and complexity. However, the ESPRIT algorithm still requires high-complexity operations such as covariance matrix and eigenvalue decomposition, so implementation with a hardware processor is essential to estimate the angle of arrival in real time. In addition, ESPRIT processors should have high performance. The performance is related to the number of antennas, and the number of antennas required for each application are different. Therefore, we proposed an ESPRIT processor that provides 2 to 8 variable antenna configurations to meet the performance and complexity requirements according to the applied field. The proposed ESPRIT processor was designed using the Verilog-HDL and implemented on a field programmable gate array (FPGA).

• The KIPS Transactions:PartC
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• v.13C no.1 s.104
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• pp.83-94
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• 2006

This paper describes ATM cell encipherment method using Rijndael Algorithm adopted as an AES(Advanced Encryption Standard) by NIST in 2001. ISO 9160 describes the requirement of physical layer data processing in encryption/decryption. For the description of ATM cell encipherment method, we implemented ATM data encipherment equipment which satisfies the requirements of ISO 9160, and verified the encipherment/decipherment processing at ATM STM-1 rate(155.52Mbps). The DES algorithm can process data in the block size of 64 bits and its key length is 64 bits, but the Rijndael algorithm can process data in the block size of 128 bits and the key length of 128, 192, or 256 bits selectively. So it is more flexible in high bit rate data processing and stronger in encription strength than DES. For tile real time encryption of high bit rate data stream. Rijndael algorithm was implemented in FPGA in this experiment. The boundary of serial UNI cell was detected by the CRC method, and in the case of user data cell the payload of 48 octets (384 bits) is converted in parallel and transferred to 3 Rijndael encipherment module in the block size of 128 bits individually. After completion of encryption, the header stored in buffer is attached to the enciphered payload and retransmitted in the format of cell. At the receiving end, the boundary of ceil is detected by the CRC method and the payload type is decided. n the payload type is the user data cell, the payload of the cell is transferred to the 3-Rijndael decryption module in the block sire of 128 bits for decryption of data. And in the case of maintenance cell, the payload is extracted without decryption processing.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.41-49
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• 2010

This paper proposes a new high speed SHA-1 architecture using multiple unfolding and pre-computation techniques. We unfolds iterative hash operations to 2 continuos hash stage and reschedules computation timing. Then, the part of critical path is computed at the previous hash operation round and the rest is performed in the present round. These techniques reduce 3 additions to 2 additions on the critical path. It makes the maximum clock frequency of 118 MHz which provides throughput rate of 5.9 Gbps. The proposed architecture shows 26% higher throughput with a 32% smaller hardware size compared to other counterparts. This paper also introduces a analytical model of multiple SHA-1 architecture at the system level that maps a large input data on SHA-1 block in parallel. The model gives us the required number of SHA-1 blocks for a large multimedia data processing that it helps to make decision hardware configuration. The hs fospeed SHA-1 is useful to generate a condensed message and may strengthen the security of mobile communication and internet service.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.11_12
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• pp.629-638
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• 2005

In the System on a Chip design, the on chip bus is one of the critical factors that decides the overall system performance. Especially, in the case or reusing the IPs such as processors, DSPs and multimedia IPs that requires higher bandwidth, the bandwidth problems of on chip bus are getting more serious. Recently ARM proposes the Multi-Layer AHB BusMatrix that is a highly efficient on chip bus to solve the bandwidth problems. The Multi-Layer AHB BusMatrix allows parallel access paths between multiple masters and slaves in a system. This is achieved by using a more complex interconnection matrix and gives the benefit of increased overall bus bandwidth, and a more flexible system architecture. However, there is one clock cycle delay for each master in existing Multi-Layer AHB BusMatrix whenever the master starts new transactions or changes the slave layers because of the Input Stage and arbitration logic realized with Moore type. In this paper, we improved the existing Multi-Layer AHB BusMatrix architecture to solve the one clock cycle delay problems and to reduce the area overhead of the Input Stage. With the elimination of the Input Stage and some restrictions on the arbitration scheme, we tan take away the one clock cycle delay and reduce the area overhead. Experimental results show that the end time of total bus transaction and the average latency time of improved Multi-Layer AHB BusMatrix are improved by $20\%\;and\;24\%$ respectively. in ease of executing a number of transactions by 4-beat incrementing burst type. Besides the total area and the clock period are reduced by $22\%\;and\;29\%$ respectively, compared with existing Multi-layer AHB BusMatrix.

• Journal of IKEEE
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• v.26 no.4
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• pp.736-741
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• 2022

Lattice-based cryptography is the most practical post-quantum cryptography because it enjoys strong worst-case security, relatively efficient implementation, and simplicity. Ring learning with errors (R-LWE) is a public key encryption (PKE) method of lattice-based encryption (LBC), and the most important operation of R-LWE is the modular polynomial multiplication of rings. This paper proposes a method for optimizing modular multipliers based on approximate computing (AC) technology, targeting the medium-security parameter set of the R-LWE cryptosystem. First, as a simple way to implement complex logic, LUT is used to omit some of the approximate multiplication operations, and the 2's complement method is used to calculate the number of bits whose value is 1 when converting the value of the input data to binary. We propose a total of two methods to reduce the number of required adders by minimizing them. The proposed LUT-based modular multiplier reduced both speed and area by 9% compared to the existing R-LWE modular multiplier, and the modular multiplier using the 2's complement method reduced the area by 40% and improved the speed by 2%. appear. Finally, the area of the optimized modular multiplier with both of these methods applied was reduced by up to 43% compared to the previous one, and the speed was reduced by up to 10%.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.109-110
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• 2014

주사전자현미경(Scanning Electron Microscopy: SEM)은 고체상태에서 미세조직과 형상을 관찰하는 데에 가장 다양하게 쓰이는 분석기기로서 최근에 판매되고 있는 고분해능 SEM은 수 나노미터의 분해능을 가지고 있다. 그리고 SEM의 초점심도가 크기 때문에 3차원적인 영상의 관찰이 용이해서 곡면 혹은 울퉁불퉁한 표면의 영상을 육안으로 관찰하는 것처럼 보여준다. 활용도도 매우 다양해서 금속파면, 광물과 화석, 반도체 소자와 회로망의 품질검사, 고분자 및 유기물, 생체시료 nnnnnnnnn와 유가공 제품 등 모든 산업영역에 걸쳐 있다(Fig. 1). 입사된 전자빔이 시료의 원자와 탄성, 비탄성 충돌을 할 때 2차 전자(secondary electron)외에 후방산란전자(back scattered electron), X선, 음극형광 등이 발생하게 되는 이것을 통하여 topography (시료의 표면 형상), morphology(시료의 구성입자의 형상), composition(시료의 구성원소), crystallography (시료의 원자배열상태)등의 정보를 얻을 수 있다. SEM은 2차 전자를 이용하여 시료의 표면형상을 측정하고 그 외에는 SEM을 플랫폼으로 하여 EDS (Energy Dispersive X-ray Spectroscopy), WDS (Wave Dispersive X-ray Spectroscope), EPMA (Electron Probe X-ray Micro Analyzer), FIB (Focus Ion Beam), EBIC (Electron Beam Induced Current), EBSD (Electron Backscatter Diffraction), PBMS (Particle Beam Mass Spectrometer) 등의 많은 분석장치들이 SEM에 부가적으로 장착되어 다양한 시료의 측정이 이루어진다. 이 중 결정구조, 조성분석을 쉽고 효과적으로 할 수 있게 하는 X선 분석장치인 EDS를 SEM에 일체화시킨 장비와 EDS 및 PBMS를 SEM에 장착하여 반도체 공정 중 발생하는 나노입자의 형상, 성분, 크기분포를 측정하는 PCDS(Particle Characteristic Diagnosis System)에 대해 소개하고자 한다. - EDS와 통합된 SEM 시스템 기본적으로 SEM과 EDS는 상호보완적인 기능을 통하여 매우 밀접하게 사용되고 있으나 제조사와 기술적 근간의 차이로 인해 전혀 다른 방식으로 운영되고 있다. 일반적으로 SEM과 EDS는 별개의 시스템으로 스캔회로와 이미지 프로세싱 회로가 개별적으로 구현되어 있지만 로렌츠힘에 의해 발생하는 전자빔의 왜곡을 보정을 위해 EDS 시스템은 SEM 시스템과 연동되어 운영될 수 밖에 없다. 따라서, 각각의 시스템에서는 필요하지만 전체 시스템에서 보면 중복된 기능을 가지는 전자회로들이 존재하게 되고 이로 인해 SEM과 EDS에서 보는 시료의 이미지의 차이로 인한 측정오차가 발생한다(Fig. 2). EDS와 통합된 SEM 시스템은 중복된 기능인 스캔을 담당하는 scanning generation circuit과 이미지 프로세싱을 담당하는 FPGA circuit 및 응용프로그램을 SEM의 회로와 프로그램을 사용하게 함으로 SEM과 EDS가 보는 시료의 이미지가 정확히 일치함으로 이미지 캘리브레이션이 필요없고 측정오차가 제거된 EDS 측정이 가능하다. - PCDS 공정 중 발생하는 입자는 반도체 생산 수율에 가장 큰 영향을 끼치는 원인으로 파악되고 있으며, 생산수율을 저하시키는 원인 중 70% 가량이 이와 관련된 것으로 알려져 있다. 현재 반도체 공정 중이나 반도체 공정 장비에서 발생하는 입자는 제어가 되고 있지 않은 실정이며 대부분의 반도체 공정은 저압환경에서 이루어지기에 이 때 발생하는 입자를 제어하기 위해서는 저압환경에서 측정할 수 있는 측정시스템이 필요하다. 최근 국내에서는 CVD (Chemical Vapor Deposition) 시스템 내 파이프내벽에서의 오염입자 침착은 심각한 문제점으로 인식되고 있다(Fig. 3). PCDS (Particle Characteristic Diagnosis System)는 오염입자의 형상을 측정할 수 있는 SEM, 오염입자의 성분을 측정할 수 있는 EDS, 저압환경에서 기체에 포함된 입자를 빔 형태로 집속, 가속, 포화상태에 이르게 대전시켜 오염입자의 크기분포를 측정할 수 있는 PBMS가 일체화 되어 반도체 공정 중 발생하는 나노입자 대해 실시간으로 대처와 조치가 가능하게 한다.