• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -3
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• pp.1567-1570
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• 2002

This paper deals with FPGA(Field Programmable Gate Array) implementation of the AAC(Advanced Audio Coding) decoder. On modern computer culture, according to the high quality data is required in multimedia systems area such as CD, DAT(Digital Audio Tape) and modem. So, the technology of data compression far data transmission is necessity now. MPEG(Moving Picture Experts Group) would be a standard of those technology. MPEG-2 AAC is the availableness and ITU-R advanced coding scheme far high quality audio coding. This MPEG-2 AAC audio standard allows ITU-R 'indistinguishable' quality according to at data rates of 320 Kbit/sec for five full-bandwidth channel audio signals. The compression ratio is around a factor of 1.4 better compared to MPEG Layer-III, it gets the same quality at 70％ of the titrate. In this paper, for a real time processing MPEG2 AAC decoding, it is implemented on FPGA chip. The architecture designed is composed of general DSP(Digital Signal Processor). And the Processor designed is coded using VHDL language. The verification is operated with the simulator of C language programmed and ECAD tool.

• 한국전자파학회논문지
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• 제14권11호
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• pp.1134-1142
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• 2003

본 논문은 STS(Space Time Spreading) 다이버시티 기능을 지원하는 시스템을 FPGA(Field Programmable Gate Array)를 이용하여 구현하고, 이 시스템을 구성하고 있는 각 모듈의 기능과 실제 설계 방법을 소개한다. 본 논문에서 구현한 개루프 전송 다이버시티 시스템인 STS 시스템의 성능을 개선하기 위해서는 페이딩 환경에 따라 변화하는 통신채널의 정확한 검출이 필수적이다. 이를 위하여 파일럿 패널의 정확한 검출을 위한 최적의 망각인자(Forgetting factor)를 제안한다. 본 논문에서 구현한 STS 시스템과 컴퓨터 시뮬레이션을 통하여 CDMA2000 1x 신호환경에서 STS 시스템 적용시 도플러 주파수 80 Hz일 경우에 0.7의 값을 가지는 망각인자를 사용하여 각 구간의 페이딩을 검출함으로써 파일럿 신호의 전력이 충분하지 않을 경우에도 적분 구간을 많이 늘릴 필요 없이 파일럿 채널을 검출할 수 있음을 알 수 있었다.

• Journal of Information Processing Systems
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• 제8권1호
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• pp.133-144
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• 2012

In order to make cognitive radio systems a practical technology to be deployed in real-world scenarios, the core Software Defined Radio (SDR) systems must meet the stringent requirements of the target application, especially in terms of performance and energy consumption for mobile platforms. In this paper we present a feasibility study of hardware acceleration as an energy-efficient implementation for SDR. We identified the amplifier function from the Software Communication Architecture (SCA) for hardware acceleration since it is one of the functions called for most frequently and it requires intensive floating-point computation. Then, we used the Virtex5 Field-Programmable Gate Array (FPGA) to perform a comparison between compiler floating-point support and the on-chip floating-point support. By enabling the on-chip floating-point unit (FPU), we obtained as high as a 2X speedup and 50% of the overall energy reduction. We achieved this with an increase of the power consumption by no more than 0.68%. This demonstrates the feasibility of the proposed approach.

• ETRI Journal
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• 제28권3호
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• pp.320-328
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• 2006

Using biometrics to verify a person's identity has several advantages over the present practice of personal identification numbers (PINs) and passwords. To gain maximum security in a verification system using biometrics, the computation of the verification as well as the storing of the biometric pattern has to take place in a smart card. However, there is an open issue of integrating biometrics into a smart card because of its limited resources (processing power and memory space). In this paper, we propose a speaker verification algorithm using a support vector machine (SVM) with a very few features, and implemented it on a 32-bit smart card. The proposed algorithm can reduce the required memory space by a factor of more than 100 and can be executed in real-time. Also, we propose a hardware design for the algorithm on a field-programmable gate array (FPGA)-based platform. Based on the experimental results, our SVM solution can provide superior performance over typical speaker verification solutions. Furthermore, our FPGA-based solution can achieve a speed-up of 50 times over a software-based solution.

• International Journal of Computer Science & Network Security
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• 제22권9호
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• pp.414-426
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• 2022

Elliptic Curve Cryptography (ECC) is one of the finest cryptographic technique of recent time due to its lower key length and satisfactory performance with different hardware structures. In this paper, a High Throughput Multiplier architecture is introduced for Elliptic Cryptographic applications based on concurrent computations. With the aid of the concurrent computing approach, the High Throughput Concurrent Computation (HTCC) technology that was just presented improves the processing speed as well as the overall efficiency of the point-multiplier architecture. Here, first and second distinct group operation of point multiplier are combined together and synthesised concurrently. The synthesis of proposed HTCC technique is performed in Xilinx Virtex - 5 and Xilinx Virtex - 7 of Field-programmable gate array (FPGA) family. In terms of slices, flip flops, time delay, maximum frequency, and efficiency, the advantages of the proposed HTCC point multiplier architecture are outlined, and a comparison of these advantages with those of existing state-of-the-art point multiplier approaches is provided over GF(2¹⁶³), GF(2²³³) and GF(2²⁸³). The efficiency using proposed HTCC technique is enhanced by 30.22% and 75.31% for Xilinx Virtex-5 and by 25.13% and 47.75% for Xilinx Virtex-7 in comparison according to the LC design as well as the LL design, in their respective fashions. The experimental results for Virtex - 5 and Virtex - 7 over GF(2²³³) and GF(2²⁸³)are also very satisfactory.

• Journal of Electrical Engineering and Technology
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• 제10권4호
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• pp.1527-1539
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• 2015

In this paper the hardware implementation of the direct torque control based on the fuzzy logic technique of induction motor on the Field-Programmable Gate Array (FPGA) is presented. Due to its complexity, the fuzzy logic technique implemented on a digital system like the DSP (Digital Signal Processor) and microcontroller is characterized by a calculating delay. This delay is due to the processing speed which depends on the system complexity. The limitation of these solutions is inevitable. To solve this problem, an alternative digital solution is used, based on the FPGA, which is characterized by a fast processing speed, to take the advantage of the performances of the fuzzy logic technique in spite of its complex computation. The Conventional Direct Torque Control (CDTC) of the induction machine faces problems, like the high stator flux, electromagnetic torque ripples, and stator current distortions. To overcome the CDTC problems many methods are used such as the space vector modulation which is sensitive to the parameters variations of the machine, the increase in the switches inverter number which increases the cost of the inverter, and the artificial intelligence. In this paper an intelligent technique based on the fuzzy logic is used because it is allows controlling the systems without knowing the mathematical model. Also, we use a new method based on the Xilinx system generator for the hardware implementation of Direct Torque Fuzzy Control (DTFC) on the FPGA. The simulation results of the DTFC are compared to those of the CDTC. The comparison results illustrate the reduction in the torque and stator flux ripples of the DTFC and show the Xilinx Virtex V FPGA performances in terms of execution time.

• Journal of Computing Science and Engineering
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• 제12권1호
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• pp.24-35
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• 2018

Deep convolutional neural network (DCNN) is an advanced technology in image recognition. Because of extreme computing resource requirements, DCNN implementation with software alone cannot achieve real-time requirement. Therefore, the need to implement DCNN accelerator hardware is increasing. In this paper, we present a field programmable gate array (FPGA)-based hardware accelerator design of DCNN targeting handwritten Hangul character recognition application. Also, we present design optimization techniques in SDAccel environments for searching the optimal FPGA design space. The techniques we used include memory access optimization and computing unit parallelism, and data conversion. We achieved about 11.19 ms recognition time per character with Xilinx FPGA accelerator. Our design optimization was performed with Xilinx HLS and SDAccel environment targeting Kintex XCKU115 FPGA from Xilinx. Our design outperforms CPU in terms of energy efficiency (the number of samples per unit energy) by 5.88 times, and GPGPU in terms of energy efficiency by 5 times. We expect the research results will be an alternative to GPGPU solution for real-time applications, especially in data centers or server farms where energy consumption is a critical problem.

• Nuclear Engineering and Technology
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• 제53권10호
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• pp.3327-3334
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• 2021

Present electric grids are advanced to integrate smart grids, distributed resources, high-speed sensing and control, and other advanced metering technologies. Cybersecurity is one of the challenges of the smart grid and nuclear plant digital system. It affects the advanced metering infrastructure (AMI), for grid data communication and controls the information in real-time. The research article is emphasized solving the nuclear and smart grid hardware security issues with the integration of field programmable gate array (FPGA), and implementing the latest Time Authenticated Cryptographic Identity Transmission (TACIT) cryptographic algorithm in the chip. The cryptographic-based encryption and decryption approach can be used for a smart grid distribution system embedding with FPGA hardware. The chip design is carried in Xilinx ISE 14.7 and synthesized on Virtex-5 FPGA hardware. The state of the art of work is that the algorithm is implemented on FPGA hardware that provides the scalable design with different key sizes, and its integration enhances the grid hardware security and switching. It has been reported by similar state-of-the-art approaches, that the algorithm was limited in software, not implemented in a hardware chip. The main finding of the research work is that the design predicts the utilization of hardware parameters such as slices, LUTs, flip-flops, memory, input/output blocks, and timing information for Virtex-5 FPGA synthesis before the chip fabrication. The information is extracted for 8-bit to 128-bit key and grid data with initial parameters. TACIT security chip supports 400 MHz frequency for 128-bit key. The research work is an effort to provide the solution for the industries working towards embedded hardware security for the smart grid, power plants, and nuclear applications.

• 융합신호처리학회논문지
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• 제13권4호
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• pp.211-219
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• 2012

본 논문에서는 VLBI상관서브시스템(VLBI Correlation Subsystem, VCS)의 상관블록 TCP/IP 출력데이터의 무결성 검사를 위한 소프트웨어의 개발과 상관출력 데이터의 손실을 방지하기 위한 성능개선 방법에 대해 기술한다. VCS의 상관결과는 TCP/IP 패킷 통신으로 데이터아카이브(Data Archive)에 저장된다. 본 논문에서는 데이터아카이브에 저장된 상관결과의 무결성을 확인하기 위해 VCS의 TCP/IP 패킷 정보를 이용한 무결성 검사 소프트웨어를 개발하였다. 개발한 소프트웨어를 이용하여 3단계의 무결성 검사 과정을 제안하고, 상관처리 실험을 통하여 제안방법의 유효성을 확인하였다. 또한 VCS와 데이터아카이브 사이에는 최소 적분시간 이내에 TCP/IP 패킷 통신이 완료되어야 하지만, 짧은 적분시간에 다량의 패킷과 대용량 데이터로 인해 패킷 손실이 발생할 뿐만 아니라 상관결과의 무결성 문제에도 영향을 미치는 것으로 확인되었다. 본 논문에서는 TCP/IP 패킷 손실의 원인을 분석하고 VCS의 FPGA(Field Programmable Gate Array) 설계에 대한 수정방법을 제시하여 상관결과의 무결성 문제를 해결하고자 한다.

• 한국인터넷방송통신학회논문지
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• 제21권6호
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• pp.49-55
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• 2021

최근 소형 추적 레이더는 다양한 환경에서 표적을 획득하고, 추적하여 한 번의 타격으로 표적의 시스템을 무능화 시킬 수 있는 높은 거리해상도를 갖는 소형 밀리미터파 추적 레이더 개발을 요구한다. 높은 거리해상도를 갖는 소형 밀리미터파 추적 레이더는 넓은 대역폭의 신호를 실시간으로 처리하고, 소형 추적 레이더의 성능 요구 조건을 충족할 수 있는 신호처리기의 구현이 필요하다. 본 논문에서는 소형 밀리미터파 추적 레이더의 신호처리기 역할과 기능을 수행할 수 있는 신호처리기를 설계하였다. 소형 밀리미터파 추적 레이더를 위한 신호처리기는 8채널에서 입력되는 OOOMHz의 중심주파수와 OOOMHz 대역폭의 신호를 실시간으로 처리하기를 요구한다. 신호처리기의 요구사항을 만족하기 위해 고성능 프로세서 및 ADC (Analog-to-digital converter) 적용과 FPGA (Field Programmable Gate Array)를 활용한 DDC (Digital Down Converter), FFT (Fast Fourier Transform) 등의 전처리 연산을 적용하여 신호처리기를 설계하였다. 마지막으로 소형 밀리미터파 추적 레이더를 위한 신호처리기의 성능시험을 통하여 구현한 신호처리기를 검증하였다.