• The Korean Journal of Applied Statistics
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• v.33 no.6
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• pp.805-812
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• 2020

High-frequency data are now prevalent in financial time series. As a functional data arising from high-frequency financial time series, we are concerned with the intraday volatility to which functional principal component analysis (FPCA) is applied in order to achieve a dimension reduction. A review on FPCA and R function is made and high-frequency KOSPI volatility is analysed as an application.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.855-858
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• 1999

In this paper, we present a FPCA implementation of IDEA algorithm. Target technology is Altera FLEX 10K FPCA. The correctness of the implementation is verified by the timing simulation with max+plus II.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.7
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• pp.1069-1072
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• 2002

고도로 발달된 정보화 시대에서 우리가 원하는 정보를 짧은 시간, 적은 비용으로 서로 주고 받기 위해서는 이것에 맞는 시스템이 요구된다. 반도체 chip의 대용량과 고속화됨으로써 TTL, ,LVTTL등이 data 100Mbps 정도를 안전하게 전달 할 수 있는 능력이 있으므로 그 이상을 전달할 수 있는 새로운 Logic level이 필요하게 되었다. 이에 맞추어 신호 level의 여러 가지 중 본 논문에서는 Virtex II XC2V 1000 FF896을 이용하여 Differential I/O LVDS( Low Voltage Differential Signaling ) level 특성을 clock, Data와의 전송관계를 Eye_Pattern을 통해 살펴보았다.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.15 no.1
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• pp.343-364
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• 2021

In the 5G era, the communication networks tend to be ultra-densified, which will improve the accuracy of indoor positioning and further improve the quality of positioning service. In this study, we propose an indoor three-dimensional (3D) dynamic reconstruction fingerprint matching algorithm (DSR-FP) in a 5G ultra-dense network. The first step of the algorithm is to construct a local fingerprint matrix having low-rank characteristics using partial fingerprint data, and then reconstruct the local matrix as a complete fingerprint library using the FPCA reconstruction algorithm. In the second step of the algorithm, a dynamic base station matching strategy is used to screen out the best quality service base stations and multiple sub-optimal service base stations. Then, the fingerprints of the other base station numbers are eliminated from the fingerprint database to simplify the fingerprint database. Finally, the 3D estimated coordinates of the point to be located are obtained through the K-nearest neighbor matching algorithm. The analysis of the simulation results demonstrates that the average relative error between the reconstructed fingerprint database by the DSR-FP algorithm and the original fingerprint database is 1.21%, indicating that the accuracy of the reconstruction fingerprint database is high, and the influence of the location error can be ignored. The positioning error of the DSR-FP algorithm is less than 0.31 m. Furthermore, at the same signal-to-noise ratio, the positioning error of the DSR-FP algorithm is lesser than that of the traditional fingerprint matching algorithm, while its positioning accuracy is higher.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.2
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• pp.355-360
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• 2005

This paper proposes bridge diagnosis system using Embedded LINUX and Genetic algorithm. The proposed system consists of MPC860 processor, FPCA, Bridge sensors and Genetic algorithm for bridge diagnosis. And the proposed system can operate with World Wide Web in GUI environment by lava, therefore, system is useful in diagnosing bridge at all times. Using genetic algorithm, this system can measure various bridge sensors with best gain and offset, therefore, range of measurement can be enlarged. Proposed system is certified by system-based test. .

• Journal of Institute of Control, Robotics and Systems
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• v.10 no.4
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• pp.371-376
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• 2004

Distributed Network Protocol Version 3.0 (DNP3.0) is the communication protocol developed for the interoperability between a RTU and a central control station of SCADA in the power utility industry. In this paper DNP3.0 is implemented by using HDL with FPGA and C program on Hitachi H8/532 processor. DNP3.0 is implemented from physical layer to network layer in hardware level to reduce the computing load on a CPU. Finally, the ASIC for DNP3.0 has been manufactured from Hynix Semiconductor. The commercial feasibility of the hardware through the communication test with ASE2000 and DNP Master Simulator is performed. The developed protocol becomes one of IP, and can be used to implement SoC for the terminal device in SCADA systems. Also, the result can be applicable to various industrial controllers because it is implemented in HDL.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.936-939
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• 2002

FPCA is the necessary device to design of hardware at present, it is researched on many ways of applying to design caused by expansion of capacity in recent years. One of these applying ways is SoC (System on a Chip) that is proposed for realizing the basic function of a system. For realizing SoC efficiently, IP (Intellectual property) is very important and developed for re-use of hardware. A MPU for built-in exists as an IP. But almost of MPUs at present as an IPs are lengthy and large-scale for using embedded-application. Furthermore, the function of executing specific treatment critically is required to embedded MPU. We propose a flexible and small scale MPU and its design method.

• Journal of the Semiconductor & Display Technology
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• v.5 no.1 s.14
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• pp.33-38
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• 2006

The ATE driver to test a high speed semiconductor chip is designed by using general logic drivers instead of dedicated pin drivers. We have proposed a structure of general logic drivers using FPCA and assured its correct operation by EDA tool simulation. PCB circuit was implemented and Altera FPGA chip was programmed using DDR I/O library. On the PCB, it is necessary to place two resistors connected output drivers near to the output pin to adjust an impedance matching. We confirmed that the measured results agree with the simulated values within 5% errors at room temperature for the input signals with 800Mbps data transfer rate and 1.8V operating voltage.

• Proceedings of the KIEE Conference
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• 2002.07d
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• pp.2783-2787
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• 2002

최근 멀티미디어 및 통신의 발달로 인하여 영상 정보를 이용한 응용시스템이 많이 연구되고있다. 중간 전달 매체를 이용한 응용시스템으로의 영상 정보를 전달과정에서 잡영(noise) 이 포함되어 시스템의 성능을 저하시키게 된다. 또한 잡영은 임의의 형태이기 때문에 상황에 따라 적합한 필터를 선택하기는 쉽지 않다. 본 논문에서는 유전자 알고리즘 프로세서를 이용하여 필터들의 구성 및 파라미터를 조절하여 임의의 잡영에 진화적응적인 능력을 가지는 영상 전처리 필터를 구현하였다. 주파수 영역의 잡영에 대해서는 하드웨어에 적합하고 구현이 용이한 멀티밴드필터(Multi-Band filter)를 설계하여 사용하였다. 시스템은 유전자알고리즘과 필터블록에 대해서는 하드웨어(FPCA)로 구현하였고 적합도 평가는 PC 기반으로 수행하였다. 실험결과 순수 PC기반의 시뮬레이션에 비해 속도향상 및 성능면에서도 만족할 만한 결과를 얻었다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.127-130
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• 2006

EPON의 상향 전송 방식에서는 다수의 ONU가 OLT로부터 공유된 채널에 대한 권한을 할당받아 데이터를 전송하게 되므로 EPON에서는 각각의 ONU들에게 공유된 대역폭을 공평하고 효율적으로 할당하기 위한 DBA 알고리즘이 필수적이다. 우리는 본 논문에 앞서 기존의 DBA알고리즘들의 문제점을 보안하여 Request-Counter Dynamic Bandwidth Assignment 알고리즘을 새롭게 제안하여 성능평가 및 비교 분석을 하였다. 본 논문에서는 제안된 RC-DBA 알고리즘을 적용하여 OLT의 MAC 스케줄러를 설계하고 Corebell 사의 LDS2000 FPCA ver.1.0 보드에 구현하였다. 또한 이를 검증하기 위해서 임베디드 리눅스 기반의 검증 시스템을 개발하였다.