• Transactions on Electrical and Electronic Materials
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• v.16 no.1
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• pp.1-4
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• 2015

(111)-oriented and random oriented $Pb_{0.8}Ba_{0.2}ZrO_3$ (PBZ) perovskite relaxor ferroelectric thin films were fabricated on Pt(111)/$TiO_x$/$SiO_2$/Si substrate by sol-gel method. Nano-scaled antiferroelectric and ferroelectric two-phase coexisted in both (111)-oriented and random oriented PBZ thin film. High dielectric tunability (${\eta}=75%$, E = 560 kV/cm) and figure-of-merit (FOM ~ 236) at room temperature was obtained in (111)-oriented thin film. Meanwhile, giant electrocaloric effect (ECE) (${\Delta}T=45.3K$ and ${\Delta}S=46.9JK^{-1}kg^{-1}$ at $598kVcm^{-1}$) at room temperature (290 K), rather than at its Curie temperature (408 K), was observed in random oriented $Pb_{0.8}Ba_{0.2}ZrO_3$ (PBZ) thin film, which makes it a promising material for the application to cooling systems near room temperature. The giant ECE as well as high dielectric tunability are attributed to the coexistence of AFE and FE phases and field-induced nano-scaled AFE to FE phase transition.

• Proceedings of the KIPE Conference
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• 2020.08a
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• pp.157-159
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• 2020

This paper presents an optimal planar transformer design of a 3-kW Low voltage DC-DC Converter (LDC) with 3.68 kW/L power density for electric vehicle (xEV) application. The transformer is optimized based on the trade-off between footprint and loss using the proposed figure-of-merit (FOM) based optimization. In order to achieve ZVS under entire load range, an external leakage inductance is added and implemented using the proposed magnetic integration technique. A comparison between non-integrated and integrated magnetic core using finite element analysis (FEA) is presented. The result shows that the integrated core can reduce the core loss up to 35 % and core boxed volume up to 15 % compared to the non-integrated core. Experimental results are also provided to validate the proposed magnetic integration technique.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.4
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• pp.295-301
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• 2008

Recently, the demand on mm-wave (millimeter-wave) applications has increased dramatically. While circuits operating in the mm-wave frequency band have been traditionally implemented in III-V or SiGe technologies, recent advances in Si MOSFET operation speed enabled mm-wave circuits realized in a Si CMOS technology. In this work, a 58 GHz CMOS LC cross-coupled VCO (Voltage Controlled Oscillator) was fabricated in a $0.13-{\mu}m$ Si RF CMOS technology. In the course of the circuit design, active device models were modified for improved accuracy in the mm-wave range and EM (electromagnetic) simulation was heavily employed for passive device performance predicttion and interconnection parasitic extraction. The measured operating frequency ranged from 56.5 to 58.5 GHz with a tuning voltage swept from 0 to 2.3 V. The minimum phase noise of -96 dBc/Hz at 5 MHz offset was achieved. The output power varied around -20 dBm over the measured tuning range. The circuit drew current (including buffer current) of 10 mA from 1.5 V supply voltage. The FOM (Figure-Of-Merit) was estimated to be -165.5 dBc/Hz.

• Proceedings of the KIEE Conference
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• 1990.07a
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• pp.451-454
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• 1990

Room temperature cw operations of a standing wave and a unidirectional Ti:Sapphire laser pumped by a $Ar^+$ laser have been demonstrated in the same pumping cavity configuration. Laser emission at 790 nm was excited with all-line $Ar^+$ laser pump for both cavities. The maximum output power was found to be 600 mW in the standing wave cavity and 210 mW in the ring cavity. Values of (83 ${\pm}$ 10) % for the internal quantum efficiency and (3.0 ${\pm}$ 0.5) % for the round-trip cavity loss for standing wave cavity are obtained from the thresholds and slope efficiencies measured with 2.4 and 11.2 % optput couplers. The measured cavity-loss value at 790 nm gives a meterial figure of merit (FOM) to be 146. Unidirectional operation of the ring Ti:Sapphire laser will be discussed.

• Journal of electromagnetic engineering and science
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• v.9 no.1
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• pp.25-31
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• 2009

This paper describes CMOS VCO circuit design procedures and techniques for multi-band/multi-standard RF transceivers. The proposed techniques enable a 4 GHz CMOS VCO to satisfy all requirements for Quad-band GSMIEDGE and WCDMA standards by achieving a good trade-off among important specifications, phase noise, power consumption, modulation performance, and chip area efficiency. To meet the very stringent GSM T/Rx phase noise and wide frequency range specifications, the VCO utilizes bond-wire inductors with high-quality factor, an 8-bit coarse tune capbank for low VCO gain(30$\sim$50 MHz/V) and an on-chip $2^{nd}$ harmonic noise filter. The proposed VCO is implemented in $0.13{\mu}m$ CMOS technology. The measured tuning range is about 34 %(3.17 to 4.49 GHz). The VCO exhibits a phase noise of -123 dBc/Hz at 400 kHz offset and -145 dBc/Hz at 3 MHz offset from a 900 MHz carrier after LO chain. The calculated figure of merit(FOM) is -183.5 dBc/Hz at 3 MHz offset. This fully integrated VCO occupies $0.45{\times}0.9\;mm^2$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.4A
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• pp.373-378
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• 2007

In this paper, the Game Theory based power control for OFDM system is studied, which has attained intensive interest as a core artificial intelligent technology for Cognitive Radio and its efficiency is evaluated using performance metrics such as system throughput and fairness. Utility Function for joint user centric and network centric power control is defined and simulation results show that game theory based power control is far better than closed loop power control. The contribution of this paper is to formalize the game theory based power control toward the Cognitive Radio that recognizes and adapts to the radio communication environments.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.581-581
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• 2013

ITO (Indium Tin oxide)는 비화학 양론적 조성을 띄는 n-type 반도체 특성이 있으며 가시광 영역(380~780 nm)의 파장에 대한 높은 광 투과도(>85%)를 가지며 비교적 높은 전도도(${\sim}10^4/{\Omega}-cm$)를 갖고 화학적 안정성이 우수하여 투명전극 박막으로 많이 사용되어왔다. 또한, PET film은 전기절연성, 내후성이 우수하고, 85%의 투과율을 보이는 특성에 의하여 Flexible display의 기판으로 많은 연구가 진행되고 있다. 이와 같은 PET film에 ITO를 증착하여 광 투과도와 전기전도도가 우수한 Flexible display의 투명전극으로 많은 연구 개발이 이루어지고 있다. Flexible ITO 박막의 특성을 향상하기 위해서는 $200^{\circ}C$ 이상의 열처리 공정이 필요하지만, PET는 약 $200^{\circ}C$ 이상에서 열 변형이 일어나므로 열처리 공정이 어렵고 이러한 문제점을 해결하기 위해 ITO/PET film에서 PET film의 변형 없이 ITO 박막의 표면에 전자빔 형태로 조사하여 박막의 물성을 개선하는 연구가 진행되고 있다 [1]. 본 연구에서는 ITO/$SiO_2$가 증착된 PET film에 전자빔을 조사하여 ITO 박막의 물성 변화를 관찰하였고, 전자빔 에너지 변화 및 전자빔 조사 시간에 따라 ITO film의 전기적, 광학적 특성 변화를 분석하였다. 구조적 특성은 XRD (X-ray diffraction), 전기적 특성은 4-point probe, Hall measurement를 이용하였으며, 가시광영역의 광 투과도는 UV-Vis spectrometer로 측정하였다. 전기 광학적 특성 변화는 Figure of Merit (FOM) 수치로 분석하였다. 이 실험으로 PET film에 직접적인 열을 가하지 않으면서 ITO 박막의 표면에 전자빔을 조사 하여, 박막의 전기전도도 및 광 투과율, 결정성 향상 등을 관찰할 수 있었다.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.191.1-191.1
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• 2013

현재 산업계 전반적으로 사용되고 있는 박막형 태양전지 투명 전도막의 재료로는 ITO 와 Al, In, Ga, B, Si, F 등으로 도핑된 ZnO 박막이 사용되고 있으며, 그 중에서도 Al 이 도핑된 ZnO 박막은 넓은 밴드갭을 가진 n-type 반도체로서, 적외선 및 가시광 영역에서의 높은 투과성과 우수한 전도성을 가지며, 고온에서 안정된 전기적 특성, 낮은 원가 등의 장점을 지녀 그 응용 연구가 활발히 이루어지고 있다 [1]. 본 연구에서는 RF magnetron Sputter 법을 이용하여 Flexible 기판 위에 AZO 박막을 증착하였다. 실험변수로는 RF power, Pressure등을 이용하였고, 최적조건에서의 박막의 투과도는 90%이상, 면저항은 30 ${\Omega}/{\square}$ 이하를 나타내었다. 그리고 (주)인포비온에서 원천기술을 갖고있는 EBA technology를 이용하여 후처리 하여 전기적, 광학적, 구조적인 특성의 변화를 관찰하였다. AZO 박막의 두께를 측정하기 위해 ${\alpha}-step$과 SEM을 이용하였고, 투과도는 UV-Vis spectrometer를 사용하여 박막의 투과도 변화를 관찰 하였다. 전기적인 특성은 4-Point probe를 이용하여 측정하였다. 또한, 박막의 결정성과 거칠기의 변화는 XRD(X-ray Diffraction)와 원자간력현미경(Atomic Force Microscope; AFM) 을 이용하여 측정하였으며, 전기 광학적 특성 변화는 Figure Of Merit(FOM) 수치로 분석하였다. 본 연구에서 AZO 박막의 특성은 EBA 조사 후 특성의 향상이 이루어지는 것을 관찰할 수 있었다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.5
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• pp.613-623
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• 2012

In this paper, we present an ultra miniaturized voltage tuned oscillator, with HMIC-type amplifier and phase shifter, using LTCC artificial dielectric resonator. ADR which consists of periodic conductor patterns and stacked layers has a smaller size than a dielectric resonator. The design specification of ADR is obtained from the design goal of oscillator. The structure of the ADR with a stacked circular disk type is chosen. The resonance characteristic, physical dimension and stack number are analyzed. For miniaturization of ADRO, the ADR is internally implemented at the upper part of the LTCC substrate and the other circuits, which are amplifier and phase shifter are integrated at the bottom side respectively. The fabricated ADRO has ultra small size of $13{\times}13{\times}3mm^3$ and is a SMT type. The designed ADRO satisfies the open-loop oscillation condition at the design frequency. As a results, the oscillation frequency range is 2.025~2.108 GHz at a tuning voltage of 0~5 V. The phase noise is $-109{\pm}4$ dBc/Hz at 100 kHz offset frequency and the power is $6.8{\pm}0.2$ dBm. The power frequency tuning normalized figure of merit is -30.88 dB.

• Journal of IKEEE
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• v.22 no.4
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• pp.1012-1018
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• 2018

In this paper, CMOS SAR (Successive Approximation Register) A/D converter with 1.8V supply voltage is designed for IoT sensor processing. This paper proposes design of a 12-bit SAR A/D converter with two A / D converters in parallel to improve the sampling rate. A/D converter1 of the two A/D converters determines all the 12-bit bits, and another A/D converter2 uses the upper six bits of the other A/D converters to minimize power consumption and switching energy. Since the second A/D converter2 does not determine the upper 6 bits, the control circuits and SAR Logic are not needed and the area is minimized. In addition, the switching energy increases as the large capacitor capacity and the large voltage change in the C-DAC, and the second A/D converter does not determine the upper 6 bits, thereby reducing the switching energy. It is also possible to reduce the process variation in the C-DAC by proposed structure by the split capacitor capacity in the C-DAC equals the unit capacitor capacity. The proposed SAR A/D converter was designed using 0.18um CMOS process, and the supply voltage of 1.8V, the conversion speed of 10MS/s, and the Effective Number of Bit (ENOB) of 10.2 bits were measured. The area of core block is $600{\times}900um^2$, the total power consumption is $79.58{\mu}W$, and the FOM (Figure of Merit) is 6.716fJ / step.