• Journal of Digital Contents Society
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• v.5 no.4
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• pp.251-256
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• 2004

The flatness of a silicon wafer concerned with ULSI chip is one of the most critical parameters ensuring high yield of wafers. That is necessary to constitute the circuit with high quality for he surface of silicon wafer, which comes to be base to make the direct circuit of the semiconductor, Flatness, therefore, is the most important factor to guarantee it wafer with high quality. The process of polishing is one of the most crucial production line among 10 processing stages to change the rough surface into the flatnees with best quality. Currently at this process, it is general for an engineer in charge to observe, judge and control the model of wafer from the monitor of measuring equipment with his/her own eyes to enhance the degree of flatness. This, however, is quite a troublesome job for someone has to check of process by one's physical experience. The purpose of this study is to approach the model of wafer with digital contents and to apply the result of the research for an algorithm which enables to control the polishing process by means of measuring the degree of flatness automatically, not by person, but by system. In addition, this paper shows that this algorithm proposed for the whole wafer flatness enables to draw an estimated algorithm which is for the thickness of sites to measure the degree of flatness for each site of wafer.

• Korean Journal of Remote Sensing
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• v.23 no.2
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• pp.113-117
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• 2007

In this paper, we propose a new method for determining automatically the size of the matching window using histogram of the gradient in order to improve the performance of stereo matching using one-meter resolution satellite imagery. For each pixel, we generate Flatness Index Image by calculating the mean value of the vertical or horizontal intensity gradients of the 4-neighbors of every pixel in the entire image. The edge pixel has high flatness index value, while the non-edge pixel has low flatness index value. By using the histogram of the Flatness Index Image, we find a flatness threshold value to determine whether a pixel is edge pixel or non-edge pixel. If a pixel has higher flatness index value than the flatness threshold value, we classify the pixel into edge pixel, otherwise we classify the pixel into non-edge pixel. If the ratio of the number of non-edge pixels in initial matching window is low, then we consider the pixel to be in homogeneous region and enlarge the size of the matching window We repeat this process until the size of matching window reaches to a maximum size. In the experiment, we used IKONOS satellite stereo imagery and obtained more improved matching results than the matching method using fixed matching window size.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2008.06a
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• pp.265-266
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• 2008

• Journal of the Chungcheong Mathematical Society
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• v.21 no.2
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• pp.287-292
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• 2008

We introduce jointly weak subnormal operators. It is shown that if $T=(T_1,T_2)$ is subnormal then T is weakly subnormal and if f $T=(T_1,T_2)$ is weakly subnormal then T is hyponormal. We discuss the flatness of weak subnormal operators.

• Journal of electromagnetic engineering and science
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• v.3 no.2
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• pp.86-90
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• 2003

A flat conversion loss in microwave mixer is hard to achieve if integrating with an image rejection filter(IRF). This is due to the change of termination condition with respect to the LO and IF frequency at RF port where the filter has 50 ohm termination property only in the RF band. This paper describes a flatness maintenance in the down mixer concerning a diode matching condition as well as an electrical length of embedding line at RF port. The implemented single balance diode mixer is suitable for a 23 ㎓ European Terrestrial Radio. RF, LO and fixed IF frequency chosen in this paper are 21.2∼22.4 ㎓, 22.4∼23.6 ㎓ and 1.2 ㎓, respectively. The measured results show a conversion loss of 8.5 ㏈, flatness of 1.2 ㏈ p-p, input P1㏈ of 7㏈m, IIP3 of 15.42 ㏈m with nominal LO power level of 10㏈m. The return loss of RF and LO port are less than - 15 ㏈ and - 12 ㏈, respectively and IF port is less than - 6 ㏈. LO/RF and LO/IF isolation are 18 ㏈ and 50 ㏈, respectively. This approach would be a helpful reference for designing up/down converter possessing a filtering element.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.17 no.2
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• pp.30-36
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• 2018

Since the freezer compartment and the refrigerating compartment are located side by side in a side-by-side refrigerator, the problems of the door height difference (DHD) and door flatness difference (DFD) have been constantly raised. Deformation of the cabinet of a built-in side-by-side refrigerator under food and thermal loads was analyzed by the finite element software ANSYS. The DHD and DFD, occurring due to the deformation of the cabinet, evaluated. From the results of the analysis of the cabinet, the 3D CAD software CATIA was used to geometrically translate and rotate the freezing and refrigerating compartment doors, in consideration of the displacement of the hinge fastening point. Then, the coordinates of two points on the upper corner of the doors were determined, and the DHD and DFD were obtained. It found that the thermal load, occurring under normal operation conditions, decreases the door height difference, but increases the door flatness difference. Values of the analyzed DHD and DFD appear smaller than the acceptance criteria used by the refrigerator manufacturer.

• Journal of Digital Contents Society
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• v.3 no.1
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• pp.113-122
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• 2002

The flatness of a silicon wafer concerned with ULSI chip is one of the most critical parameters ensuring high yield of wafers. The polishing process that measures and controls the flatness of a silicon wafer is one of the important process in various processes for production silicon wafer, which are still being done today by manual. But engineers in polishing process are requested to have many experiences and to check silicon wafers one by one. In this paper, we propose an algorithm used interpolation that estimates wafer's shape and sorts wafers automatically, then we can control the flatness of wafers in polishing process by automatic system.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.8
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• pp.1572-1579
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• 2009

In this dissertation ultra-broadband power amplifier(UPA) was designed and fabricated using negative feedback technique. UPA was made of pre-amplifier, drive amplifier and power amplifier. Negative feedback technique was used to achieve ultra-broadband performance. Designed power amplifier has 30dB gain and 2W output power. The load-pull data of power amplifier for optimal power matching was extracted from the measured S-parameter. Fabricated PCB material, permittivity is 4.6 and thickness is 0.8mm, is FR4 and UPA was fabricated 3 modules for comparison of the simulated and measured results. Size of the fabricated pre-amplifier and drive amplifier module is 40mm'50mm'16mm. And from the experimental results, gain of the pre-amplifier module is 9.87dB at 2GHz and flatness is 0.63dB. Experimental result of the drive amplifier module is 10.97dB at 2GHz and flatness of that is 0.26dB. Test result of the power amplifier module is 10.71dB at 2GHz and flatness is 0.72dB. Total size of the power amplifier is 45mm'134mm'16mm. According to the test results, gain of the UPA is 28.98dB at 2GHz and flatness is 1.68dB. Output power was 32.098dBm at 2GHz, 32.154dBm at 1GHz and 31.273dBm at 100MHz.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.31 no.8
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• pp.847-854
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• 2007

The battery electrode of a mobile phone is made of layered polymer coated on aluminum foils and the hot rolling process is applied to increase the density per volume of an electrode for a high capacity battery. The flatness of batteries surfaces should be less than $2{\mu}m$. To satisfy the required flatness, the deformation of roll surface due to bending and heating of the roll should be minimized. Complicated hot oil paths of $100^{\circ}C$ inside the roll are required for heating the polymer layers. FEA was used to calculate thermal deformations and temperatures distributions of the roller. Based on FEA, a modified surface curvature called a crown roll was suggested and this gave the area of 30% improved flatness compared with a flat roll. The flat roll satisfied the flatness of $2{\mu}m$ in the length of 340 mm and the crown roll resulted in the longer length of 460 mm. Experiments to measure the temperature distribution and thermal strain were performed and compared with FEA. There were only 6% difference between two results.

• International Journal of Precision Engineering and Manufacturing
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• v.8 no.2
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• pp.64-69
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• 2007

Aerostatic planar XY stages are frequently used as the main frames of precision positioning systems. The machining and assembly process of the rails and bed of the stage is one of first processes performed when the system is built. When the system is complete, the 2D position, motion, and stage flatness errors are measured in tests. If the stage errors exceed the application requirements, the stage must be remachined and the assembly process must be repeated. This is difficult and time-consuming work. In this paper, a method for estimating the errors of a planar XY stage is proposed that can be applied when the rails and bed of the stage are evaluated. Profile measurements, estimates of the motion error, and 2D position estimation models were considered. A comparison of experimental results and our estimates indicated that the estimated errors were within $1{\mu}m$ of their true values. Thus, the proposed estimation method for 2D position and flatness errors of an aerostatic planar XY stage is expected to be a useful tool during the assembly process of guideways.