• Journal of Electrical Engineering and information Science
• /
• v.1 no.1
• /
• pp.160-163
• /
• 1996

New formulas for McClellan transform parameters for the design of 2-D zero-phase FIR fan filters are optimally derived under the integral squared error(ISE) criterion. By imposing the constraint that F(0, 0)=\ulcorner, where F($.$) is the McClellan transform and $\omega$\ulcorner is the cutoff frequency of the 1-D prototype filter, the ISE is directly minimized without modifying it and, as a consequence, closed-form formulas for the McClellan transform parameters are obtained. It is shown that these formulas lead to a very efficient design for 2-D zero-phase FIR fan filters.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.15 no.8
• /
• pp.1687-1694
• /
• 2011

In this paper, we propose the design procedure of a digital IF system for the OFDM based WLAN system and examine its performances. Along with the decision procedure of ADC sample rate, NCO frequency and the required decimation ratio, we show the decimation ratio is accomplished through the use of a CIC filter and a MHBF. We also show that the amplitude distortion occurred in the decimation filters can effectively be compensated by a ISOP filter and an additional FIR filter, which leads to the reduction of the overall hardware complexity. Finally, we examine the BER performance of the proposed system and compare it with a theoretical one that excludes filter non-linearities.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.5 no.4
• /
• pp.630-638
• /
• 2001

This paper has been proposed a structure composed of FIRs and IIR filters as digital decimation filter to compensate the drooping inband on the high precision AU chips. The area of chip has been reduced compared with the conventional structure because the RAM and MAC is reduced. The passband ripple$(\leq\; 0.4535 \times fs)$, passband attenuation(at $\; 0.4535 \times fs$ and stopband attenuation$(\geq\; 0.59\times fs)$ of the 6th-order $\Delta\Sigma$ modulator and digital decimation filter had $\pm0.0007[dB]$, -0.0013[dB] and -110[dB] respectively. Also the inband group delay, which was almost same compared with the conventional digital decimation filter structure, was 30.07/fs[s] band the error of group delay was 0.1672%.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.40 no.3
• /
• pp.93-98
• /
• 2003

With the improvement of digital signal processors, digital pulse compressor(DPC) is widely used in radar systems. The DPC can be implemented by using FIR filter algorithm in time domain or FFT algorithm in frequency domain. This paper designs an expansible DPC using multiple DSPs. With ADSP-21060 of Analog Devices Inc., the computation time as a function of the number of received range cells and FIR filter tap is compared and analyzed in time domain using C-language and assembly language. therefore, when radar system parameters are determined, the number of DSP's required to implement DPC can be easily estimated.

• Proceedings of the KIEE Conference
• /
• 2003.07a
• /
• pp.345-347
• /
• 2003

본 논문에서는 디지털 보호 계전기에 쓰이는 필터 중에서 최소 자승 알고리즘을 이용한 고성능 FIR 필터를 설계하였다. 기존의 DFT필터와 MATLAB 시뮬레이션을 이용하여 비교하였으며 FIR 필터의 VHDL모델 및 합성에 중점을 두었다. FIR 필터는 기본적으로 유한개의 임펄스 응답이 이루어지기 때문에 기타 다른 필터에 비하여 안정도가 높으며 선형적인 위상을 가지기 때문에 차단 주파수 대역의 왜곡현상을 없앨 수 있는 장점을 가지고 있다. 여러 가지 알고리즘으로 구현한 FIR 필터를 시뮬레이션 한 결과 최소 자승 알고리즘이 가장 우수한 결과를 나타내었다. 기본적으로 디지털 보호 계전기에서 디지털 필터의 기능은 사고 전압, 전류로부터 60Hz의 기본파 추출 CT, PT 왜곡 및 DC offset을 제거하는데 있다. 본 논문에서는 이러한 기능을 가지면서 샘플링 주파수와 차수를 같게 하여 FIR 필터와 DFT 필터의 주파수 응답과 연 산 속도를 비교 하였다. 본 논문에서 설계된 최소 자승 알고리즘을 이용한 FIR 필터는 같은 조건의 DFT필터에 비해 1고조파와 2고조파의 차이가 10db 이상 더 우수 하였으며 연산 속도 또한 2배 이상 좋은 결과를 보였다.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.12 no.11
• /
• pp.2039-2044
• /
• 2008

The problem of an efficient hardware implementation of multiple constant multiplication is frequently encountered in many digital signal processing applications such as FIR filter and linear transform (e.g., DCT and FFT). It is known that efficient solutions based on common subexpression elimination (CSE) algorithm can yield significant improvements with respect to the area and power consumption. In this paper, we present an efficient specialized adder design method for two common subexpressions ($10{\bar{1}}$, 101) in canonic signed digit (CSD) coefficients. By Synopsys simulations of a radix-24 FFT example, it is shown that the proposed method leads to about 21%, 11% and 12% reduction in the area, propagation delay time and power consumption compared with the conventional methods, respectively.

• Journal of Industrial Technology
• /
• v.28 no.B
• /
• pp.129-133
• /
• 2008

A method to reduce seam line artifact in spatial compounding of ultrasonic images is presented. Spatial compounding is a speckle reducing imaging technique in which a number of ultrasound images of a given target that have been obtained from multiple view angles are combined into a single compounded image by combining the data received from each data point in the compounded image. Since different view angle results in different view area, and the images of different view arms are combined into an image, the compounded image consists of regions with different signal to noise ratio, and the boundary lines between these regions are visible as seam lines in the compounded images. In this paper, we present an algorithm that reduces the visibility of this seam line in the spatially compounded images. Design procedure for a FIH filter is described and the results of applying the filter to in-vivo ultrasonic images are analyzed.

• Journal of Electrical Engineering and Technology
• /
• v.13 no.6
• /
• pp.2479-2484
• /
• 2018

The filter bank multicarrier modulation (FBMC) technique is one of multicarrier modulation technique (MCM), which is mainly used to improve channel capacity of cognitive radio (CR) network and frequency spectrum access technique. The existing FBMC System contains serial to parallel converter, normal QAM modulation, Radix2 inverse FFT, parallel to serial converter and poly phase filter. It needs high area, delay and power consumption. To further reduce the area, delay and power of FBMC structure, a new clock gating technique is applied in the QAM modulation, radix2 multipath delay commutator (R2MDC) based inverse FFT and unified addition and subtraction (UAS) based FIR filter with parallel asynchronous self time adder (PASTA). The clock gating technique is mainly used to reduce the unwanted clock switching activity. The clock gating is nothing but clock signal of flip-flops is controlled by gate (i.e.) AND gate. Hence speed is high and power consumption is low. The comparison between existing QAM and proposed QAM with clock gating technique is carried out to analyze the results. Conversely, the proposed inverse R2MDC FFT with clock gating technique is compared with the existing radix2 inverse FFT. Also the comparison between existing poly phase filter and proposed UAS based FIR filter with PASTA adder is carried out to analyze the performance, area and power consumption individually. The proposed FBMC with clock gating technique offers low power and high speed than the existing FBMC structures.

• Journal of Sensor Science and Technology
• /
• v.15 no.4
• /
• pp.223-230
• /
• 2006

An FIR filter for digital voice signal processing has been designed and implemented using a microcontroller in implantable middle ear hearing devices (IMEHDs). The designed digital voice signal processing filter which has fast and accurate filtering operation and controllable filter characteristics has been implemented using a hardware multiplier and a direct memory access (DMA) in the low power microcontroller, MSP430F169. It has been confirmed that each of the implemented 6-orders Remez FIR filters with 1 channel and 2 channels can be applied to the voice signal processing module of IMEHDs based on the evaluation results of the filtering performance experiment.

• ETRI Journal
• /
• v.25 no.5
• /
• pp.345-355
• /
• 2003

In this paper, we propose a method for designing a class of M-channel, causal, stable, perfect reconstruction, infinite impulse response (IIR), and parallel uniform discrete Fourier transform (DFT) filter banks. It is based on a previously proposed structure by Martinez et al. [1] for IIR digital filter design for sampling rate reduction. The proposed filter bank has a modular structure and is therefore very well suited for VLSI implementation. Moreover, the current structure is more efficient in terms of computational complexity than the most general IIR DFT filter bank, and this results in a reduced computational complexity by more than 50% in both the critically sampled and oversampled cases. In the polyphase oversampled DFT filter bank case, we get flexible stop-band attenuation, which is also taken care of in the proposed algorithm.