• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.37 no.11
• /
• pp.85-95
• /
• 2000

FIR digital filter is one of important blocks in DSP application. For more effective operation, lots of architecture are proposed. In our paper, we proposed a high speed FIR filter with area efficiency. To fast operation, we used transposed form filter as basic architecute. And, we used dual path registers line to wupport variation of filter operation, and filter cascade is also considered. To reduce area, we adopted truncated Booth multiplier to our filter design. As a result, we showed that filter area is reduced when filter optimization using of dual path registers line and truncated multiplier with same constraints againt previous method.

• Proceedings of the KIEE Conference
• /
• 2005.10b
• /
• pp.309-311
• /
• 2005

In general, for specific applications, customized hardware showed better performance than general processor in terms of processing time and power consumption. However, customized hardware systems have lacks of flexibility in nature and it leads the difficulties for debugging and architecture level revision for performance enhancement. To solve this problem, reconfigurable hardware is developed. Proposed reconfigurable hardware architecture for FIR filter system can easily change the architecture of filter blocks including filter tap size and their signal path. Proposed FIR filter architecture was implemented on FPGA using several MUXs and registers and it showed the reconfigurablility and reusability in several examples.

• Proceedings of the KIEE Conference
• /
• 2005.10b
• /
• pp.502-504
• /
• 2005

Recently genetic algorithm techniques have widely used in adaptive and control schemes for production systems. However, generally it costs a lot of time for learning in the case applied in control system. Furthermore, the physical meaning of genetic algorithm constructed as a result is not obvious. And this method has been used as a learning algorithm to estimate the parameter of a genetic algorithm used for identification of the process dynamics of FIR filter and it was shown that this method offered superior capability over the genetic algorithm. A genetic algorithm is used to solve the parameter identification problem for linear and nonlinear digital filters. This paper goal estimate FIR filter parameter using the genetic algorithm.

• 제어로봇시스템학회:학술대회논문집
• /
• 2000.10a
• /
• pp.521-521
• /
• 2000

This paper investigates the problem of robust H$_{\infty}$ filter with FIR(Finite Impulse Response) structure for linear continuous time-varying systems with sampled-data measurements. It is assumed that the system is subject to real time-varying uncertainty which is represented by the state-space model having parameter uncertainty. The robust H$_{\infty}$ FIR filter is proposed for the continuous-time linear parameter uncertain systems. It is also derived from the equivalence relationship between the robust linear H$_{\infty}$ FIR filter and the robust linear H$_{\infty}$ filter with sampled-data measurements.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.8
• /
• pp.32-36
• /
• 2008

Multiplierless FIR filters can be designed by only adders using Common Subexpression algorithm. It has small area compared with filter which using multipliers. But it has long operation time because of carry ripple from the adder. In this paper, when the subexpressions are added in multiplier less filters, the number of subexpressions maintains 2 until final addition to avoid carry ripple of the addition, so the subexpression addition time of the filter can be reduced. To verify proposed method, subexpression adder circuit of the FIR filter is designed using given example of paper. The designed filter was synthesized using Hynix 0.18um process. By Synopsys simulation results, it is shown that by the proposed method, area, propagation delay time can be reduced up to 53.2%, 57.9% compared with conventional design method which using pipeline.

• Journal of Broadcast Engineering
• /
• v.16 no.1
• /
• pp.174-177
• /
• 2011

In this paper, we investigate a method for designing FIR filters with CSD coefficients. Firstly, the H/W complexity of a CSD FIR filter is estimated in terms of number of gates. Using the estimated complexity, an optimal filter that can meet the required performance with minimal H/W complexity can be designed. Next, based on the MILP problem solver called BonsaiG, we present a filter design program. From the two design examples, it is demonstrated that an optimal filter can be obtained by comparing the complexity of the candidate filters in terms of the gate counts, whose differences are estimated to be about 400-600 gates.

• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.31B no.9
• /
• pp.22-26
• /
• 1994

In this paper a method of designing FIR filters without digital arithmetic operationsi is persented. The filter coefficients are represented by resistors combined with a differential amplifier. With this method an FIR filter can be simply impemented without refering to complex digital arithmetic operations. Furthermore, in this scheme, no additional D/A converter is needed for D/A conversion. Spectral response response of a pulse shaping filter of 17 coefficients is shown as an illustration.

• 제어로봇시스템학회:학술대회논문집
• /
• 1987.10b
• /
• pp.690-693
• /
• 1987

Base-line wandering and 60Hz noise in ECG are removed by linear phase FIR filter. The important problem in FIR filtering is to reduce the number of impulse response coefficients. It can be reduced by symmetrical impulse response. The ripple is improved by window function .omega.(n). And the determination of filter accuracy is proposed by PRD(percent rms difference) algorithm.

• Proceedings of the KIEE Conference
• /
• 1988.07a
• /
• pp.567-570
• /
• 1988

This paper describes the design of FIR filtering DSP-chip that can be operated without programming. The proposed DSP-chip has not only the improvement of execution time but also selectivity of filter length from N=1 to N=128. Hilbert Transformer can be designed from this chip. FIR filter system is composed of Data memory/Control Unit, external memory and multiplier-accumulator. Data memory/Control Unit is laid out in this paper.

• Proceedings of the Korea Committee for Ocean Resources and Engineering Conference
• /
• 2004.05a
• /
• pp.386-389
• /
• 2004

Beamforming for underwater acoustic communication is affected by the broadband feature of underwater acoustic communication signal, which has the low center frequency compared to the signal bandwidth. In this paper, the baseband equivalent array signal model is derived and we present computer simulation results for the broadband finite impulse response (FIR) beamformer performance according to the FIR filter order and the tap spacing. If the FIR filter order is increased above the optimum value, the beamformer performance is degraded. Also the tap spacing is related to the optimum FIR filter order.