• Journal of the Institute of Electronics Engineers of Korea SP
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• v.37 no.5
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• pp.115-123
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• 2000

In this paper, a block FIR(Finite Impulse Response) filtering architecture is proposed for IF digital down converter. Digital down converter consists of digital mixers. decimation filters and down samplers. In this proposed structure, it is shown that a efficient parallel decimation filter architecture can be produced by cancellation of inherent up sampling of the block filter and following down sampler Furthermore. it is shown that computational complexity of the proposed architecture is reduced by exploiting the block FIR structure and zero values of the digital mixers.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.3
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• pp.105-112
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• 2007

In general, the earlier methods for the design of MAXFLAT FIR filters have existent problems due to the approximation algorithms used to approach MAXFLAT(maximally flat) response in the passband and the stopband.. The proposed approach advanced by using of MAXSHCUT(maximally sharp cutoff) condition in this paper clearly overcomes these problems. In this approach, we use a key parameter represented with filter-order and cutoff-frequency parameters for obtaining the lowpass filters with the MAXFLAT and MAXSHCUT characteristics in the frequency domain. Consequently, this design technique leads to new MAXFLAT and MAXSHCUT FIR digital filter, which can achieve sharp-cutoff responses with the stopband attenuation exceeding 100 dB almost everywhere.

• Proceedings of the KIEE Conference
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• 2005.10b
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• pp.502-504
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• 2005

Recently genetic algorithm techniques have widely used in adaptive and control schemes for production systems. However, generally it costs a lot of time for learning in the case applied in control system. Furthermore, the physical meaning of genetic algorithm constructed as a result is not obvious. And this method has been used as a learning algorithm to estimate the parameter of a genetic algorithm used for identification of the process dynamics of FIR filter and it was shown that this method offered superior capability over the genetic algorithm. A genetic algorithm is used to solve the parameter identification problem for linear and nonlinear digital filters. This paper goal estimate FIR filter parameter using the genetic algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.2
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• pp.166-175
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• 1990

The conventional FIR filters can be very expensive to implement due to the complexity of multibit multipliers. This paper presents an new type of multiplierless structure which is particularly suited to the hardware implementation of small, low cost, low power, high speed digital filters. The filter structures consisting of a transversal filter with tap coefficiented to the combination of two elements of the set {0, $\pm$$2^n$;n = integer} and cascaded with a integrator are proposed. Performance has been tested via simulation on a digital computer, and the results show that the response characteristics of presented filters are as equally good as those of conventional finitewordlength filters.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.5A
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• pp.494-499
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• 2008

In this study, a Software Defined Radio(SDR) technology-based digital filtering technique applicable to a multiple channel processing system such as a wireless mobile communication system using Code Division Multiple Access(CDMA) technology is proposed. The technique includes a micro-processor to redesign Finite Impulse Response(FIR) filter coefficients according to specific system information and to download the filter coefficients to one digital Band Pass Filter(BPF) to reconfigure another system. The feasibility of the algorithm is verified by implementing a multiple channel signal generator that is reconfigurable to other system profiles, including those for a CDMA system and a WCDMA system on identical hardware platform.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.12
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• pp.2046-2054
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• 1989

Improved algorithms are presented to design linear phase digital FIR filters with coefficients of +1,0,-1 only followed by a multiple integrator. It has been shown that the existing linear phase filter design concept for the single integrator(or, accumulator)case can be extended to the case of the multiple integrator. Linear phase conditions for the multiple integrators are summarized. Filter design methods with double or triple integrator are exploited in datail and its computer simulation results are presented to deduce the advantages of multiple integrator to the single integrator.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.10 no.6
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• pp.327-334
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• 1985

A new method on the hardware implementation of multi-channel Finite Impulse Response(FIR) digital filter using vector multiplication structure is proposed. The proposed method can reduce the complexity of hardware structure and improve execution speed. The frequency response of four channel digital filter implemented by the above method is quite agreeable with the frquency response simulated by Remez method.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.10
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• pp.2375-2381
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• 2014

In case the coefficient set of an FIR filter is represented in the canonic signed digit (CSD) format with a few nonzero digits, it is possible to implement high data rate digital filters with low hardware cost. Designing an FIR filter with CSD format coefficients, whose number of nonzero signed digits is minimal, is equivalent to finding sparse nonzero signed digits in the coefficient set of the filter which satisfies the target frequency response with minimal maximum error. In this paper, a compressive sensing based CSD coefficient FIR filter design algorithm is proposed for multiplierless and high speed implementation. Design examples show that multiplierless FIR filters can be designed using less than two additions per tap on average with approximate frequency response to the target, which are suitable for high speed filtering applications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.4
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• pp.97-102
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• 2007

This paper presents our implemented, synthesized and tested on demand and partial reconfiguration approaches for FIR filters using Xilinx Virtex FPGAs. Our scope is implementation of a low-power, area-efficient autonomously reconfigurable digital signal processing architecture that is tailored for the realization of arbitrary response FIR filters on Xilinx Virtex4 FPGAs. The implementation of design addresses area efficiency and flexibility allowing dynamically inserting and/or removing the partial modules to implement the partial reconfigurable FIR filters with various taps. This partial reconfigurable FIR filter design shows the configuration time improvement, good area efficiency and flexibility by using the dynamic partial reconfiguration method.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1986.04a
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• pp.78-80
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• 1986