• Proceedings of the KIPE Conference
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• 2007.07a
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• pp.476-478
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• 2007

This paper presents an efficient data acquisition scheme to obtain a minimum CPU memory, optimized communication speed, and simplified program source code in a monitoring system. It is different in the number of utilized data from the conventional method which acquires every raw data. The proposed method uses only restrictive data required to reconstruct the original signal. The basic principle is to apply the FFT-IFFT method in data transferring process. To verify the high-performance of the proposed scheme, computer-aided simulation and experiments using a PV power monitoring system are carried out. It also presents the analyzed results the relationship between FFT's order and Gibb's Phenomenon.

• The Journal of the Korea institute of electronic communication sciences
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• v.3 no.2
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• pp.86-92
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• 2008

Othogonal Frequency Division Multiplexing(OFDM) has been taken notice of 4th generation communication method because it has a merit of high data rate(HDR). To realize HDR communication, The OFDM a s high efficient Fast-Fourier-Transform (FFT)/Inversion FFT (IFFT) processor. Currently OFDM is realized by Digital Signal Processor(DSP) but it consumes a lot of Power. Therefore, current-mode FFT LSI has been proposed for compensation of this demerit. In this paper, we propose IVC for current-mode FFT LSI. From the simulation result, the output value of IVC is more than 3V when the value of FFT Block output is more than $7.35{\mu}A$. The output value of IVC is lower than 0.5V when the value of FFT Block output is lower than $0.97{\mu}A$. Designed IVC Low-power Current mode FFT LSI will contribute to the operation of current-mode FFT LSI and the development of next generation wireless communication systems.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.10a
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• pp.499-503
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• 2000

The use of Multiple-Valued FFT(Fast fourier Transform) is extended from binary to multiple-valued logic(MVL) circuits. A multiple-valued FFT circuit can be implemented using current-mode CMOS techniques, reducing the transitor, wires count between devices to half compared to that of a binary implementation. For adder processing in FFT, We give the number representation using such redundant digit sets are called redundant positive-digit number representation and a Redundant set uses the carry-propagation-free addition method. As the designed Multiple-valued FFT internally using PD(positive digit) adder with the digit set 0,1,2,3 has attractive features on speed, regularity of the structure and reduced complexities of active elements and interconnections. for the mutiplier processing, we give Multiple-valued LUT(Look up table)to facilitate simple mathmatical operations on the stored digits. Finally, Multiple-valued 8point FFT operation is used as an example in this paper to illuatrates how a multiple-valued FFT can be beneficial.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.48 no.4
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• pp.53-60
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• 2011

In order to augment the robustness of OFDM system to Rayleigh multipath fading, there exist two smart antenna algorithms, namely, Pre-FFT smart antenna and Post-FFT smart antenna. After the mathematical modeling of both smart antenna algorithms, computer simulations have been carried to compare and analyze the performance of generalized eigen problem based Pre-FFT algorithm and the performance of Wiener solution based Post-FFT algorithm. It has been shown that the Post-FFT smart antenna far outperforms the Pre-FFT smart antenna due to the computational complexities. Especially it is so when the multipath signal arrives at beyond the guard interval and a rich co-channel interferer is introduced. Performance of a subcarrier clustering method proposed to lessen the computing load has been compared to that of a typical Wiener solution based Post-FFT smart antenna. Performance comparison between MRC(Maximum Ratio Combining) diversity based Post-FFT algorithm and typical Post-FFT algorithm has also been carried.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.5
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• pp.32-38
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• 2009

FTT(Fast Fourier Transform) processor is widely used in OFDM(Orthogonal Frequency Division Multiplesing) system. Because of the increased requirement of mobility and bandwidth in the OFDM system, they need large point FTT processor. Since the size of memory which stores the twiddle factor coefficients are proportional to the N of FFT size, we propose a new method by which we can reduce the size of the coefficient memory. In the proposed method, we exploit a counter and unsigned multiplier to generate the twiddle factor indices. To verify the proposed algorithm, we design TFCGs(Twiddle Factor Coefficient Generator) for 1024pint FFTs with R2SDF(Radix-2 Single-Path Delay Feedback), $R2^3SDF,\;R2^3SDF,\;R2^4SDF$ architectures. The size of ROM is reduced to 1/8N. In the case of $R2^4SDF$ architecture, the area and the power are reduced by 57.9%, 57.5% respectively.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.113-116
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• 2002

This paper describes a design of 8192-Point pipelined FFT/IFFT processor (PFFTSk) core for DVB-T and DMT-based VBSL modems. A novel two-step convergent block floating -point (75_CBFP) scaling method is proposed to improve the signal- to-quantization-noise ratio (SeNR) of FFT/IFFT results. Our approach reduces about 80% of memory when compared with conventional CBFP methods. The PFFTSk core, which is designed in VHDL and synthesized using 0.25-${\mu}{\textrm}{m}$ CMOS library, has about 76,300 gates, 390k bits RAM, and Twiddle factor ROM of 39k bits. Simulation results show that it can safely operate up to 50-MHz clock frequency at 2.5-V supply, resulting that a 8192-point FFT/IFFT can be computed every 164-$mutextrm{s}$. The SQNR of about 60-dB is achieved.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.5
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• pp.475-480
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• 2018

In OFDM-based systems, FFT is a critical component since it occupies large area and consumes more power. In this paper, we present a low hardware-cost and low power 512-point pipelined FFT design method for OFDM applications. To reduce the number of twiddle factors and to choose simple design architecture, the radix-$2^4-2^3$ algorithm are exploited. For twiddle factor multiplication, we propose a new canonical signed digit (CSD) complex multiplier design method to minimize the hardware-cost. In hardware implementation with Intel FPGA, the proposed FFT design achieves more than about 28% reduction in gate count and 18% reduction in power consumption compared to the previous approaches.

• 제어로봇시스템학회:학술대회논문집
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• 1996.10b
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• pp.1384-1387
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• 1996

SCPI(Standard Commands for Programmable Instrument) is a standard command sets designed for controlling various types of instruments. In order to control FFT(Fast Fourier Transform) analyzing device using SCPI it is required to support sweep measurement function. We defined SCPI command set for FFT analysis and developed parser of defined command set using lex(Lexical Analyzer Generator) and yacc(Yet Another Compiler Compiler). After developing FFT analyzing test was performed with that parser. Up to audible signal frequency the result of FFT analysis was accurate and that result was agree with that of conventional FFT analyzer. As a result it is proved that various types of instruments including sweep measurement instrument can be controlled with appropriate SCPI command sets. Also when developing new instruments the method used in this experiment will contribute to reducing the time required to develop the SCPI parser and increasing reliability.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.5
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• pp.12-25
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• 1994

A two dimensional constant geometry FFT algorithms and architectures with shuffled inputs and normally ordered outputs are presented. It is suitable for VLSI implementation because all buterfly stages have identical, regular structure. Also a methodology using shuffled FFT inputs and outputs to halve the number of butterfly stages connected by a global interconnection which requires much area is presented. These algorithms can be obtained by shuffling the row and column of a decomposed FFT matrix which corresponds to one butterfly stage. Using non-recursive and recursive pipeline, the degree of serialism and parallelism in FFT computation can be adjusted. To implement high performance high radix FFT easily and reduce the amount of interconnections between stages, the method to build a high radix PE with lower radix PE 's is discussed. Finally the performances of the present architectures are evaluated and compared.

• Structural Engineering and Mechanics
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• v.14 no.4
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• pp.417-434
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• 2002

This paper explores the possibility of using a combination of the empirical mode decomposition (EMD) and the Hilbert transform (HT), termed the Hilbert-Huang transform (HHT) method, to identify the modal damping ratios of the structure with closely spaced modal frequencies. The principle of the HHT method and the procedure of using the HHT method for modal damping ratio identification are briefly introduced first. The dynamic response of a two-degrees-of-freedom (2DOF) system under an impact load is then computed for a wide range of dynamic properties from well-separated modal frequencies to very closely spaced modal frequencies. The natural frequencies and modal damping ratios identified by the HHT method are compared with the theoretical values and those identified using the fast Fourier transform (FFT) method. The results show that the HHT method is superior to the FFT method in the identification of modal damping ratios of the structure with closely spaced modes of vibration. Finally, a 36-storey shear building with a 4-storey light appendage, having closely spaced modal frequencies and subjected to an ambient ground motion, is analyzed. The modal damping ratios identified by the HHT method in conjunction with the random decrement technique (RDT) are much better than those obtained by the FFT method. The HHT method performing in the frequency-time domain seems to be a promising tool for system identification of civil engineering structures.