• Journal of IKEEE
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• v.16 no.3
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• pp.189-196
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• 2012

This paper proposes new phase error compensation method of RVDT encoder in the FFT domain. Phase errors are measured with a small combination of compensation resistors and the changes of first order coefficients of FFT for each resistor are obtained. It is found that the coefficient change is inversely proportional to the inserted resistor. The proposed method takes less time and the size of the table is smaller than previous time domain approaches. In addition, the location of the compensation resistor can be found through axis transformation of the coefficients. Finally, the peak-to-peak phase error was improved to 0.57 which is two times better than previous one.

• Journal of Electrical Engineering and Technology
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• v.8 no.6
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• pp.1380-1388
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• 2013

The conventional graphical representation of the instantaneous compensation power flow for single-phase active power filters(APFs) simply represents the active power flow and the reactive power flow which flowing between the power source and the active filter / the load. But, this method does not provide the information about the rectification mode and the compensation mode of APFs, especially, the loss for each mode was not considered at all. This is very important to understand the compensation operation characteristics of APFs. Therefore, this paper proposes the graphical representation of the instantaneous compensation power flow for single-phase APFs considering the instantaneous rectification mode and the instantaneous inversion mode. Three cases are verified in this paper - without compensation, with compensation of the active power 'p' and the fundamental reactive power 'q', and with compensation of only the distorted power 'h'. To ensure the validity of the proposed approach, PSIM simulation is achieved. As a result, we could confirm that the proposed approach was easy to explain the instantaneous compensation power flow considering the instantaneous rectification mode and the instantaneous inversion mode of APFs, also, Total Harmonic Distortion(THD)/Power Factor (P.F) and Fast Fourier Transform(FFT) analysis were compared for each case.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.41 no.1
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• pp.41-54
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• 2004

In this paper, we propose a new digital hearing aid circuit that compensates the impaired threshold level changing nonlinearly using a multi-band compensation technique. In the algorithm the hearing frequency range 8kHz is divided into 64 bands which is 125Hz resolution. Each band is controlled finely to compensate the hearing impaired proportional to personal ROM table. The multi-band is introduced using a FFT/IFFT Processor which makes to control in frequency domain. As a result, the proposed circuit is more efficient $15\%$ than a conventional ones such as FIR filter architecture in terms of the compensation gun and accuracy. The hardware size was reduced $65\%$ than a general FFT by pre-handling of the input data.

• The Journal of the Korea institute of electronic communication sciences
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• v.3 no.2
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• pp.86-92
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• 2008

Othogonal Frequency Division Multiplexing(OFDM) has been taken notice of 4th generation communication method because it has a merit of high data rate(HDR). To realize HDR communication, The OFDM a s high efficient Fast-Fourier-Transform (FFT)/Inversion FFT (IFFT) processor. Currently OFDM is realized by Digital Signal Processor(DSP) but it consumes a lot of Power. Therefore, current-mode FFT LSI has been proposed for compensation of this demerit. In this paper, we propose IVC for current-mode FFT LSI. From the simulation result, the output value of IVC is more than 3V when the value of FFT Block output is more than $7.35{\mu}A$. The output value of IVC is lower than 0.5V when the value of FFT Block output is lower than $0.97{\mu}A$. Designed IVC Low-power Current mode FFT LSI will contribute to the operation of current-mode FFT LSI and the development of next generation wireless communication systems.

• Journal of Advanced Marine Engineering and Technology
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• v.27 no.7
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• pp.914-920
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• 2003

In this paper, we deal with two drift compensation algorithms of acceleration sensor for measuring the galloping on power transmission line. Firstly, the block diagram of galloping measurement system is given and a galloping model is presented. Secondly, two compensation algorithms, a simple compensation and a period compensation, are proposed. A simple compensation algorithm uses the drifts of velocity and distance at fixed periods, so it is useful for constant drift case. Next, a period compensation algorithm can compensate a periodic drift. This algorithm uses the previous measured data and compensated data for constant period, where the period is obtained by FFT method. Lastly, the effectiveness of proposed algorithms is verified by comparing between two algorithms in simulation, and its characteristics and the drift error bound are shown, respectively.

• Journal of Power Electronics
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• v.10 no.4
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• pp.412-418
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• 2010

This paper proposes a new algorithm to generate a reference signal for an active power filter using a sliding-window FFT operation to improve the steady-state performance of the active power filter. In the proposed algorithm the sliding-window FFT operation is applied to the load current to generate the reference value for the compensating current. The magnitude and phase-angle for each order of harmonics are respectively averaged for 14 periods. Furthermore, the phase-angle delay for each order of harmonics passing through the controller is corrected in advance to improve the compensation performance. The steady-state and transient performance of the proposed algorithm was verified through computer simulations and experimental work with a hardware prototype. A single-phase active power filter with the proposed algorithm can offer a reduction in THD from 75% to 4% when it is applied to a non-linear load composed of a diode bridge and a RC circuit. The active power filter with the proposed reference generation method shows accurate harmonic compensation performance compared with previously developed methods, in which the THD of source current is higher than 5%.

• Journal of Power Electronics
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• v.12 no.3
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• pp.509-517
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• 2012

This paper presents control strategies for cascaded H-bridge multilevel active power filters (APFs). A current loop controller is implemented using a proportional-resonant (PR) regulator, which achieves zero steady-state error at target frequencies. The power balancing mechanism for the dc-link capacitor voltages is analyzed and a voltage balancing controller is presented. To mitigate the picket-fence effect of the conventional FFT algorithm under asynchronous sampling conditions, the Hanning Windowed-FFT algorithm is proposed for reference current generation (RCG). This calculates the frequency, amplitude and phase of individual harmonic components accurately and as a result, selective harmonic compensation (SHC) is achieved. Simulation and experimental results are presented, which verify the validity and effectiveness of the devised control algorithms.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.127.6-127
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• 2001

In this paper, we deal with two bias compensation algorithms of acceleration sensor for measuring the galloping on power transmission line. Firstly, the block diagram of galloping measurement system is given and a galloping model is presented. Secondly, two compensation algorithms, a simple compensation and a period compensation, are proposed. A simple compensation algorithm use the drafts of velocity and distance at fixed periods, so it is useful for constant bias case. Next, a period compensation algorithm can compensate a periodic bias. This algorithm use the previous measured data and compensated data for constant period, where the period is obtained by FFT method. Lastly, the effectiveness of proposed algorithms is verified by comparing between two algorithms in simulation, and its characteristics and the bias error bound are shown, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.33-38
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• 2009

The group CSD (GCSD) multiplier was recently proposed based on the variation of canonic signed digit (CSD) encoding and partial product sharing. This multiplier provides an efficient design when the multiplications are performed only with a few predetermined coefficients (e.g., FFT). In many DSP applications such as FFT, the (2W-1)-bit product obtained from W-bit multiplicand and W-bit multiplier is quantized to W-bits by eliminating the (W-1) least-significant bits. This paper presents an error compensation method for a fixed-width GCSD multiplier that receives a W-bit input and produces a W-bit product. To efficiently compensate for the quantization error, the encoded signals from the GCSD multiplier are used for the generation of error compensation bias. By Synopsys simulations, it is shown that the proposed method leads to up to 84% reduction in power consumption and up to 79% reduction in area compared with the fixed-width modified Booth multiplier.

• Journal of the Institute of Convergence Signal Processing
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• v.14 no.2
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• pp.136-146
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• 2013

In this paper, the residual delay compensation algorithm is proposed for FX-type KJJVC. In case of initial version as that design algorithm of KJJVC, the integer calculation and the cos/sin table for the phase compensation coefficient were introduced in order to speed up of calculation. The mismatch between data timing and residual delay phase and also between bit-jump and residual delay phase were found and fixed. In final design of KJJVC residual delay compensation algorithm, the initialization problem on the rotation memory of residual delay compensation was found when the residual delay compensated value was applied to FFT-segment, and this problem is also fixed by modifying the FPGA code. Using the proposed residual delay compensation algorithm, the band shape of cross power spectrum becomes flat, which means there is no significant loss over the whole bandwidth. To verify the effectiveness of proposed residual delay compensation algorithm, we conducted the correlation experiments for real observation data using the simulator and KJJVC. We confirmed that the designed residual delay compensation algorithm is well applied in KJJVC, and the signal to noise ratio increases by about 8%.