• Title/Summary/Keyword: FFT 방법

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A 8192-Point FFT Processor Based on the CORDIC Algorithm for OFDM System (CORDIC 알고리듬에 기반 한 OFDM 시스템용 8192-Point FFT 프로세서)

  • Park, Sang-Yoon;Cho, Nam-Ik
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.27 no.8B
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    • pp.787-795
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    • 2002
  • This paper presents the architecture and the implementation of a 2K/4K/8K-point complex Fast Fourier Transform(FFT) processor for Orthogonal Frequency-Division Multiplexing (OFDM) system. The architecture is based on the Cooley-Tukey algorithm for decomposing the long DFT into short length multi-dimensional DFTs. The transposition memory, shuffle memory, and memory mergence method are used for the efficient manipulation of data for multi-dimensional transforms. Booth algorithm and the COordinate Rotation DIgital Computer(CORDIC) processor are employed for the twiddle factor multiplications in each dimension. Also, for the CORDIC processor, a new twiddle factor generation method is proposed to obviate the ROM required for storing the twiddle factors. The overall 2K/4K/8K-FFT processor requires 600,000 gates, and it is implemented in 1.8 V, 0.18 ${\mu}m$ CMOS. The processor can perform 8K-point FFT in every 273 ${\mu}s$, 2K-point every 68.26 ${\mu}s$ at 30MHz, and the SNR is over 48dB, which are enough performances for the OFDM in DVB-T.

FFT에 기반한 병렬 디지털 신호처리시스템의 성능분석

  • 박준석;전창호;박성주;이동호;오원천;한기택
    • The Journal of the Acoustical Society of Korea
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    • v.18 no.1
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    • pp.3-9
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    • 1999
  • This paper concerns performance of a parallel digital signal processing system. The performance of the system is analyzed in terms of CPU cycles required for 1024-point FFT computation. The number of cycles is estimated in three different approaches; FFT algorithm-based, assembly level source code-based, and probability-based. The results of analysis indicate that on a bus-based system the best performance for FFT is achieved with a single board. Because in some applications like FFT, where frequent data exchanges among processors occur, the number of communication cycles increases as the number of boards. It is observed that inter-board communication degrades overall system performance for the FFT computation. Also shown is that linear increase in performance can be obtained if multiple buses are employed.

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An Efficient Computation of FFT for MPEG/Audio Psycho-Acoustic Model (MPEG 심리음향모델의 고속 구현을 위한 효율적 FFT 연산)

  • 송건호;이근섭;박영철;윤대희
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.41 no.6
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    • pp.261-269
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    • 2004
  • In this paper, an efficient algorithm for computing in the MPEG/audio Layer Ⅲ (MP3) encoder is proposed. The proposed algerian performs a full-band 1024-point FFT by computing 32-point FFT's of 32 subband outputs. To reduce the aliasing caused by the analysis filter bank, an aliasing cancellation butterfly is developed. A major benefit of the proposed algorithm is the computational saving. By using the proposed algorithm, it is possible to save 40~50% of computations for FFT, which results in about 20% reduction of the PAM-2 complexity.

Radix-2 16 Points FFT Algorithm Accelerator Implementation Using FPGA (FPGA를 사용한 radix-2 16 points FFT 알고리즘 가속기 구현)

  • Gyu Sup Lee;Seong-Min Cho;Seung-Hyun Seo
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.34 no.1
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    • pp.11-19
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    • 2024
  • The increased utilization of the FFT in signal processing, cryptography, and various other fields has highlighted the importance of optimization. In this paper, we propose the implementation of an accelerator that processes the radix-2 16 points FFT algorithm more rapidly and efficiently than FFT implementation of existing studies, using FPGA(Field Programmable Gate Array) hardware. Leveraging the hardware advantages of FPGA, such as parallel processing and pipelining, we design and implement the FFT logic in the PL (Programmable Logic) part using the Verilog language. We implement the FFT using only the Zynq processor in the PS (Processing System) part, and compare the computation times of the implementation in the PL and PS part. Additionally, we demonstrate the efficiency of our implementation in terms of computation time and resource usage, in comparison with related works.

A Study on the variable points IFFT/FFT processor (재구성 가능한 가변 포인트 IFFT/FFT 프로세서 설계에 관한 연구)

  • Choi Won-Chul;Goo Jeon-Hyoung;Lee Hyun;Oh Hyun-Seo
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.41 no.12
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    • pp.61-68
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    • 2004
  • Wireless mobile communication systems request high speed mobility and high speed data transmission capability. In order to meet the requirements, OFDM(Orthogonal Frequency Division Multiplex) is mainly adopted in the physical layer of the wireless systems. In commercial wireless mobile systems, IEEE802.(11a, 16e, etc) series seem to be used as the modulation method. For supporting multiple air-interfaces in a wireless mobile system, different kinds of OFDM based modulation methods should be supported in one modem chip. It requires a variable point IFFT/FFT or reconfigurable IFFT/FFT processor. In this paper, we propose the design method of a reconfigurable IFFT/FFT processor. In addition, it is shown that a reconfigurable IFFT/FFT processor can he implemented by using the proposed method.

New DIT Radix-8 FFT Butterfly Structure (새로운 DIT Radix-8 FFT 나비연산기 구조)

  • Jang, Young-Beom
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.16 no.8
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    • pp.5579-5585
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    • 2015
  • In FFT(Fast Fourier Transform) implementation, DIT(Decimation-In-Time) and DIF (Decimation-In-Frequency) methods are mostly used. Among them, various DIF structures such as Radix-2/4/8 algorithm have been developed. Compared to the DIF, the DIT structures have not been investigated even though they have a big advantage producing a sequential output. In this paper, a butterfly structure for DIT Radix-8 algorithm is proposed. The proposed structure has smaller latency time because of Radix-8 algorithm in addition to the advantage of the sequential output. In case of 4096-point FFT implementation, the proposed structure has only 4 stages which shows the smaller latency time compared to the 12 stages of Radix-2 algorithm. The proposed butterfly can be used in FFT block required the sequential output and smaller latency time.

Feature detection of peaks of sound signal using MEM (최대 엔트리법을 이용한 음향 신호의 특징 피크의 검출)

  • 성종훈;김영길
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 1998.11a
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    • pp.562-564
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    • 1998
  • 보통 음향 신호를 분석을 할 때에 시간영역의 신호를 주파수영역의 신호로 FFT 변환을 해서 분석을 한다. 이렇게 단순히 FFT를 해서 주파수영역의 신호에서 어떤 특징적인 점을 찾기가 매우 어렵다. 그래서 원 신호를 FFT를 하지 않고 선형 예측 분석이라는 방법을 적용하여 신호에 특징적인 피크 점들을 구하면 쉬운 방법이 된다. 본 논문에서는 이러한 음향의 신호를 분석을 할 때에 선형 예측 분석법을 이용하면 신호에서 특징적인 피크들을 구하기가 용이함을 보이고 신호의 특징 피크 점들을 통계적으로 처리하여 분석을 해보았다.

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FFT of Deep Ocean Simulation (FFT를 이용한 깊은 바다 시뮬레이션)

  • 양은주;김은주;유관우
    • Proceedings of the Korean Information Science Society Conference
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    • 2003.10b
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    • pp.664-666
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    • 2003
  • 본 논문에서는 해양학의 관찰을 통한 통계학적 모델과 영상처리 기법을 이용하여 바다 표면을 나타내는 방법을 제시한다. 파도를 구성하는 파들의 합을 모두 구하지 않고, 높이필드를 사용하여 FFT로 처리하는 것은 전체적인 파도를 한꺼번에 빠르고 쉽게 모델링 할 수 있다는 장점을 가진다. 또한 통계적 모델을 적용할 때, 영상처리에 사용하는 필터를 사용하여 보다 자연스러운 물결을 표현하는 방법을 제시한다. 그리고 주파수 영역에서 매그니튜드 값의 효율적인 사용법을 제시하여 파도의 애니메이션을 나타낸다.

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Improvement of resolution to finite Band using ZOOM FFT (특정 대역 신호의 주파수 성분 분석을 위한 ZOOM FFT 기법)

  • Park, Chong-Yeun;Cho, Gye-Hyun
    • Proceedings of the KIEE Conference
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    • 2000.07d
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    • pp.3091-3093
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    • 2000
  • FFT 알고리즘은 DC 성분에서부터 나이퀴스트 주파수까지 주파수 성분에 관한 해석이며, 주파수 정밀도는 DC 성분에서부터 나이퀴스트 주파수까지의 샘플 수에 의존했다. 하지만 많은 경우, 특정한 주파수 대역에 대한 주파수 정보를 보다 정확하게 분석하고자 하는 상황이 나타난다. 이렇게 특정 주파수 대역에 대해서 확장된 분석을 수행하는 것을 Zoom FFT라 한다. 하지만, 이러한 Zoom FFT를 수행한다 할지라도 FFT 알고리즘이 가지는 특성상 입력 신호가 가지는 정확한 주파수 성분을 얻는다는 것은 불 가능하다. 본 논문에서는 Zoom FFT를 수행하는 방법과 수행했을 때 발생하는 에러에 관해서 다룬다.

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Efficient Implementation of IFFT and FFT for PHAT Weighting Speech Source Localization System (PHAT 가중 방식 음성신호방향 추정시스템의 FFT 및 IFFT의 효율적인 구현)

  • Kim, Yong-Eun;Hong, Sun-Ah;Chung, Jin-Gyun
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.46 no.1
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    • pp.71-78
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    • 2009
  • Sound source localization systems in service robot applications estimate the direction of a human voice. Time delay information obtained from a few separate microphones is widely used for the estimation of the sound direction. Correlation is computed in order to calculate the time delay between two signals. In addition, PHAT weighting function can be applied to significantly improve the accuracy of the estimation. However, FFT and IFFT operations in the PHAT weighting function occupy more than half of the area of the sound source localization system. Thus efficient FFT and IFFT designs are essential for the IP implementation of sound source localization system. In this paper, we propose an efficient FFT/IFFT design method based on the characteristics of human voice.