• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.4
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• pp.484-491
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• 2008

In this paper, we design and fabricate the L-band high speed pulsed HPA using LDMOS FET. And we propose the high voltage and high speed switching circuit for LDMOS FET. The pulsed HPA using LDMOS FET is simpler than using GaAs FET because it has a high gain, high output power and sin81e voltage supply. LDMOS FET is suitable for pulsed HPA using switching method because it has $2{\sim}3$ times higher maximum drain-source voltage(65 V) than operating drain-source voltage($V_{ds}=26{\sim}28\;V$). As results of test, the output peak power is 100 W at 1.2 GHz, the rise/fall time of output RF pulse are 28.1 ns/26.6 ns at 2 us pulse width with 40 kHz PRF, respectively.

• Proceedings of the KIPE Conference
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• 2019.07a
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• pp.279-280
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• 2019

본 논문에서는 3KW급 전력변환장치에 적용 가능한 650V급 GaN FET를 사용하여 Half-bridge 구조의 개발보드를 설계 및 제작하고, Double pulse test 실험을 통해 Turn-on 및 off 시스위칭 특성을 분석하였다. 또한 동기정류식 Buck 컨버터에 GaN FET을 적용하고, 유사한 전압 및 전류 정격의 Si MOSFET 소자와 시스템 효율을 비교하여 GaN FET 전력반도체의 성능을 평가하였다.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.2
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• pp.18-23
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• 1992

Recently, SSPAs(Solid-State Power Amplifiers) with high linearity and efficiency replace TWTAs (Traveling-Wave-Tube Amplifiers) in satellite transponders. In this paper, a power amplifier with maximum output power is designed and constructed using GaAs FET(MGF-1302) as a test model for the development of SSPAs. For conjugate matching of input and output network, transimission lines and stubs are optimized using microwave CAD program, LINMIC+. Power amplifier is realized on the teflon substrate($\in$S1rT=2.45) with a bandwidth of 1GHz at a center frequency of 8GHz. Maximum stable gain of simulation and simulation and experimental result is obtained 9.23, 7.65 dB, respectively.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.5
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• pp.358-365
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• 2016

We propose a novel application of random forest, a machine learning-based general classification algorithm, to analyze the influence of design attributes on the silicon-to-SPICE (S2S) gap. To improve modeling accuracy, we introduce magnification of learning data as well as randomization for the counting of design attributes to be used for each tree in the forest. From the automatically generated decision trees, we can extract the so-called importance and impact indices, which identify the most significant design attributes determining the S2S gap. We apply the proposed method to actual silicon data, and observe that the identified design attributes show a clear trend in the S2S gap. We finally unveil 10nm key fin-shaped field effect transistor (FinFET) structures that result in a large S2S gap using the measurement data from 10nm test vehicles specialized for model-hardware correlation.

• Journal of Korean Society on Water Environment
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• v.28 no.6
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• pp.943-953
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• 2012

Because of their unique properties, nano-sized metallic nanomaterials (NMs) have been used in extensive applications of biomedicine, electronics, optics, engineering, and personal care products. Accordingly, with the increasing release of NMs into the environment, numerous studies of nanoecotoxicity have been conducted. Fish embryo toxicity test (FET) has many benefits in evaluating toxicity of NMs as an alternative to a whole-body test in fish. In this study, we collected and analyzed the toxicity studies of metallic NMs on freshwater fish embryos. Most studies have demonstrated that metallic NMs are highly toxic during the early development of fish embryos. However, it should be noted that the results for the same NMs on the same test species show variation due to differences in the size or surface properties of the test NMs and exposure conditions. For the safe use of metallic NMs, we need to analyze their effects based on their properties, test species, environmental media, and diverse conditions.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.5
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• pp.123-127
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• 2017

This paper fabricated and analyzed the image rejection mixer that uses FET's channel resistance. It can be applied for capacity 64QAM that has 50MHz~90MHz of IF band, 8.17GHz of LO frequency and 8.08~8.12GHz of RF band. When IF input power is -20dBm and LO input power is 10dBm, RF output power is obtained -33.2dBm. In this case, conversion loss is 12.9dB, the suppression of 14.3dB for LO frequency and 10.4dB for image frequency. The result of two tone test shows great IMD characteristics with 51.7dBc.

• Journal of Electrical Engineering and information Science
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• v.2 no.6
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• pp.202-207
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• 1997

Design and fabrication issues for an L-band GaAs Monolithic Microwave Integrated Circuit(MMIC) Voltage Controlled Oscillator(VCO) as a component of Personal Communications Systems(PCS) Radio Frequency(RF) transceiver are discussed. An ion-implanted GaAs MESFET tailored toward low current and low noise with 0.5mm gate length and 300mm gate width has been used as an active device, while an FET with the drain shorted to the source has been used as the voltage variable capacitor. The principal design was based on a self-biased FET with capacitive feedback. A tuning range of 140MHz and 58MHz has been obtained by 3V change for a 600mm and a 300mm devices, respectively. The oscillator output power was 6.5dBm wth 14mA DC current supply at 3.6V. The phase noise without any buffer or PLL was 93dB/1Hz at 100KHz offset. Harmonic balance analysis was used for the non-linear simulation after a linear simulation. All layout induced parasitics were incorporated into the simulation with EEFET2 non-linear FET model. The fabricated circuits were measured using a coplanar-type probe for bare chips and test jigs with ceramic packages.

• Journal of IKEEE
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• v.26 no.4
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• pp.553-559
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• 2022

In this paper, RC snubber circuit design technology for oscillation suppression in half-bridge configuration of cascode gallium nitride (GaN) field effect transistors (FETs) is analyzed. A typical wide band-gap (WBG) device, cascode GaN FET, has excellent high-speed switching characteristics. However, due to such high-speed switching characteristics, a false turn-off problem is caused, and an RC snubber circuit is essential to suppress this. In this paper, the commonly used experimental-based RC snubber design technique and the RC snubber design technique using the root locus method are compared and analyzed. In the general method, continuous circuit changes are required until the oscillation suppression performance requirement is met based on experimental experience . However, in root locus method, the initial value can be set based on the non-oscillation R-C map. To compare the performance of the two aforementioned design methods, a simulation experiment and a switching experiment using an actual double pulse circuit are performed.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.11
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• pp.6821-6829
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• 2014

The use of semiconductor devices as a component of eco-friendly motor vehicles has increased and their widespread use as high voltage switches is expected. On the other hand, in the case of high-voltage switches, reliability test equipment is not localized. To test high voltage switches, this paper analyzed the relevant test standards for developing power supplies. In particular, for the automotive semiconductor reliability test, the AEC (Automotive Electronic Council) Q101 was analyzed. Based on that, the standard specifications of the power supply were determined. For the main power circuit, the pull bridge converter was adopted and based on the specification, the circuit parameters were determined and verified by simulation. The interface for the parallel and pattern operation was designed. The characteristics of the power supply were tested.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.2
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• pp.63-75
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• 1993

As the CMOS technology becomes the most dominant circuit realization method, the cost problem for the test which includes both the transistor-level FET stuck-on and stuck-off faults and the gatelevel stuck-at faults becomes more and more serious. In accordance, this paper proposes a test set and its generation algorithm, which handles both the transistor-level faults and the gate-level faults, thus can unify the test steps during the IC design and fabrication procedure. This algorithm uses only the logic equation of the given logic function as the input resource without referring the transistor of gate circuit. Also, the resultant test set from this algorithm can improve in both the complexity of the generation algorithm and the time to apply the test as well as unify the test steps in comparing the existing methods.