• 대한전자공학회논문지SD
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• 제38권3호
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• pp.12-12
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• 2001

PLZT(10/30/70), PLT(10) 및 PZT(30/70) 와 같은 강유전체 박막의 이력곡선을 field-dependent polarization 모델을 이용하여 시뮬레이션하고, 측정한 실험적 결과와 비교, 분석하였다. PZT(30/70) 박막의 경우, 5V 이상의 인가전압에서 분극의 포화현상이 둔감하게 나타나고 시뮬레이션 값과의 차이도 심해 강유전체 분극이 순수한 dipole 외에도 다양한 전하의 영향을 받아 형성된다는 사실을 알 수 있다. 또, quasi-MFISFET 소자의 드레인 전류는 field-dependent polarization 모델의 강유전체 이력곡선에서 얻은 파라미터를 square-law FET 모델에 적용시켜 효과적으로 추출하였고, 모델링 결과는 실험값과 유사하였다. 그리고, quasi-MFISFET 소자의 gate 에 -10V의 ′write′ 전압을 인가한 상태에서 PZT(30/70) 박막을 사용한 경우, PLZT(10/30/70), PLT(10) 박막 보다 빨리 채널이 형성되었는데, 그 원인은 강유전체 박막에 따른 retention 특성에서 PZT(30/70) 박막의 분극 감소가 PLZT(10/30/70), PLT(10) 박막의 분극 감소 보다 약 3∼4 배 이상 크다는 점에서 찾을 수 있다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권3호
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• pp.170-172
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• 2002

The epilayer of vertically stacked, self-assembled InAs Quantum Dots (QDs)was grown by MBE with solid sources in non-cracking K-cells, and the sample was fabricated to a FET structure using a conventional technology. The device characteristic and performance were studied. At 77K and room temperature, the threshold voltage shift values are 0.75V and 0.35 V, which are caused by the trapping and detrapping of electrons in the quantum dots. Discharging and charging curves form the part of a hysteresis loop to exhibit memory function. The electrical injection of confined electrons in QDs products the threshold voltage shift and memory function with the persistent electron trapping, which shows the potential use for a room temperature application.

• 한국광학회:학술대회논문집
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• 한국광학회 1998년도 제15회 광학 및 양자전자 학술발표회 논문집
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• pp.192-193
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• 1998

At Rutherford Appleton Laboratory(RAL), a high-repetition rate ps exicmer laser-plasma x-ray source has been developed for x-ray lithography with a calibrated output of up to 1 watt X-ray average power at 1nm wavelength. In a previous reports this compact x-ray source was used to print 0.18$\mu$m lines for a gate on Si-FET devices and deep three-dimensional structure with 100$\mu$m length, 25$\mu$m width, and 48 $\mu$m depth for a nanotechnology. The deep X-ray lithography is called as LIGA thchnology and getting a wide interest as a new technology for a nano-device. In this report all this works are summarized.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 하계학술대회 논문집 C
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• pp.1579-1581
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• 1996

The high temperature characteristics of SOI BMFET are analyzed by the numerical simulation and compared with MOS-gated SOI power devices at high temperatures. The proposed SOI BMFET combines bipolar operation in the on-state with unipolar FET operation in the off-state, so that it may be suitable for high temperature operation without any significant degradation of performance such as the leakage current and blocking capability. The simulation results show that SOI BMFET with a higher doped n-resurf layer is the most promising device far high temperature application as compared with MOS-gated SOI power devices, exhibiting the low on-state voltage drop as well as the excellent forward blocking capability at high temperature.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2010년도 춘계학술발표대회
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• pp.25.1-25.1
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• 2010

본 연구에서는 절연막에 삽입시킨 실리콘 나노와이어 유연소자를 제작하고 그 소자의 전기적 특성을 분석하여 유연소자로서의 적합성을 평가하였다. 최근 반도체 및 디스플레이 등이 다양한 현장에 응용되면서 유연성을 이용한 소자의 필요성이 대두되고 있다. 이러한 요구를 바탕으로 나노와이어를 유연소자에 적용시키기 위하여 삽입방법을 이용하여 field-effect transistor(FET) 소자를 제작하였다. 유연소자의 기판으로는 polyimide(PI) 및 poly(ethylene 2,6 naphtahalate)(PEN)을 사용하였고, 절연막은 poly-4-vinylphenol(PVP)을 이용하였으며 이때, 나노와이어는 무전해 식각법으로 합성한 실리콘 나노와이어를 사용하였다. 이렇게 제작된 유연소자를 휨 상태 및 삽입된 정도에 따른 전기적 특성을 비교하였고 휨 테스트를 통하여 소자의 안정성을 분석하였다. 전기적 특성은 I-V 측정을 통하여 Ion/Ioff ratio, 이동도, subthreshold swing, threshold voltage값 등을 평가하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1988년도 전기.전자공학 학술대회 논문집
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• pp.356-359
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• 1988

An FET type urea sensing device has been developed using the ISFET and platinum reference electrode and by employing the differential amplification. The performance characteristics of the fabricated sensor show a good linearity in the urea concentration range of $5{\times}10^{-5}$ to $10^{-3}$g/ml and a stable response.

• 대한전자공학회논문지
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• 제16권2호
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• pp.24-34
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• 1979

반도체 소자의 모델에 대한 특성을 비교하고 체제적인 모데링 기법에 대하여 논하였다. 체계적인 모데링 기법을 이용한 FET의 선형 및 비선형 모델을 구하고 모델을 이용하여 과도해석하는 프로그램을 개발하였다.

• 반도체디스플레이기술학회지
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• 제13권4호
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• pp.43-48
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• 2014

Two-level inverter has some disadvantages like high harmonics contained in the output current, efficiency limit and stress to switching device as IGBT and FET. Many researches have reported multi-level inverter to complement two-level inverter of problems. In this paper, we suggest MPPT algorithm of multi-string three-level solar inverter that considered nowadays. We added midpoint controller in order to implement the MPPT algorithm because the three-level inverter has to need midpoint controller and procured the stability of direct current link. We verify the superiority of multi-string T-Type inverter and the algorithm we suggested with solar irradiance variation experiment and MPPT efficiency measurement. The MPPT efficiency was confirmed with a high efficiency more than 99.97%.

• 한국전기전자재료학회논문지
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• 제19권6호
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• pp.558-562
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• 2006

We have synthesized a new p-type polymer, poly(9,9'-n-dioctylfluorene-alt-phenoxazine) (PFPO), via the palladium catalyzed coupling reaction. The number average molecular weight ($M_n$) of PFPO was found to be 23,000. PFPO dissolves in common organic solvents such as chloroform and toluene. The UV-visible absorption maximum of the PFPO thin film is clearly blue-shifted with respect to that of F8T2, poly-(9,9'-n-dioctylfluorene-alt-bithiophene). The introduction of the phenoxazine moiety into the polymer system results in better field-effect transistor (FET) performance than that of F8T2. A solution processed PFPO TFT device with a top contact geometry was found to exhibit a hole mobility of $2.7{\times}10^{-4}cm^2/Vs$ and a low threshold voltage of -2 V with high on/off ratio(${\sim}10^4$).

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 하계학술대회 논문집 C
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• pp.1955-1957
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• 2003

This paper presents a novel defected ground structure (DGS) and its application to a microwave oscillator. The presented oscillator is designed so as to use the suggested defected ground structure as a feedback loop inducing a negative resistance as well as a frequency-selective circuit. Applying the feedback loop between the drain and the gate of a FET device produces precise phase conversion in the feedback loop. The equivalent circuit parameters of the DGS are extracted by using a three-dimensional EM calculations and simple circuit analysis method. The implemented 1.07 GHz oscillator exhibits 0 dBm output power with over 15% dc-to-RF power efficiency and -106 dBc/Hz phase noise at 100 kHz offset from carrier.