• Title/Summary/Keyword: FDE

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Performance Analysis by Secondary link Frame structure in UAV System (무인기 운용환경을 고려한 보조링크 프레임 구조설계에 따른 성능분석)

  • Yoon, Chang-Bae;Kim, Hoi-Jun;Hong, Su-Woon
    • The Journal of the Korea institute of electronic communication sciences
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    • v.12 no.6
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    • pp.1115-1120
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    • 2017
  • In this paper, we apply the LMMSE(: Linear Minimum Mean Square Error) algorithm to overcome the Doppler effect according to the UAV(: Unmanned Aerial Vehicle) velocity in multipath fading channel environment. Simulation results show that the performance difference depends on the pilot arrangement and pattern, and we confirmed that the frame structure proposed in this paper can provide a stable secondary link for high speed UAV system.

On the Application of Cyclic Delay Diversity to Distributed SC-FDMA Systems (분산할당 SC-FDMA 시스템에서의 순환지연 다이버시티의 적용)

  • Rim, Min-Joong
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.45 no.12
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    • pp.49-57
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    • 2008
  • In distributed-allocation OFDMA systems, cyclic delay diversify can improve the system performance by increasing frequency diversity. However, applying cyclic delay diversify to distributed-allocation SC-FDMA systems can affect the performance in two contrary ways: positive effect due to increased frequency diversity and negative effect caused by increased frequency selective channels. This paper addresses these two contrary effects and discusses about when cyclic delay diversity is useful and when it is not very useful for distributed-allocation SC-FDMA systems.

A Study on Performance of Symbol Error Rate for Frequency Domain Eqaulization (수중 무선채널환경에서 주파수영역 등화기법의 심볼오율에 대한 연구)

  • Hwang, Ho-Seon;Park, Kyu-Tae;Shin, Kee-Cheol;Cho, Sung-Il
    • Journal of the Institute of Convergence Signal Processing
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    • v.18 no.2
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    • pp.37-42
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    • 2017
  • In this paper, we study on symbol error rate(SER) performance of frequency domain decision feedback equalization for modelled underwater channel. Underwater channel is generated by Bellhop model. Simulation results show that proposed method is efficient for underwater acoustic communication.

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Modeling of Fuzzy Discrete Event System using Fuzzy Temporal Logic (퍼지 시간논리를 이용한 퍼지 이산사건시스템의 모델링)

  • Kim, Jin-Kwon;Kim, Jung-Chul;Hang, yung-Soo
    • Proceedings of the KIEE Conference
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    • 2003.07d
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    • pp.2292-2294
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    • 2003
  • 본 논문은 crisp discrete event system(CDES)에서 다룰 수 없는 특성을 가지는 의료진단이나 교통제어와 같이 애매하거나 불확실한 판단 그리고 관련성이 모호한 판단의 근거들에 의해 결정되어지는 사건들로 이루어진 fuzzy discrete event system(FDES)의 모델링 방법에 대하여 연구하였다. CDES는 모델링 방법이 많이 연구되어져 왔으나, FDES는 발생되어지는 사건들의 정성적인 특성과 적용되어지는 경우가 드문 이유로 거의 연구되어져 있지 않다. 본 논문에서는 temporal logic에 fuzzy개념을 도입하여 fuzzy DES의 새로운 모델링 방법을 제시하고 의료진단 시스템에 적용하였다.

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Measurement of the Device Properties of Photoelectric Smoke Detector for the Fire Modeling (화재모델링을 위한 광전식 연기감지기의 장치물성 측정)

  • Cho, Jae-Ho;Mun, Sun-Yeo;Hwang, Cheol-Hong;Nam, Dong-Gun
    • Fire Science and Engineering
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    • v.28 no.6
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    • pp.62-68
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    • 2014
  • The high predictive performance of fire detector models is essentially required for the reliable design of evacuation safety using the fire modeling. The main objective of the present study is to measure input information in order to predict the accurate activation time of photoelectric smoke detector adopted in fire dynamics simulator (FDS) recognized a representative fire model. To end this, the fire detector evaluator (FDE) which could be measured the device properties of detector was used, and the input information of Heskestad and Cleary's models was obtained for a spot-type photoelectric smoke detector. In addition, the activation times of smoke detector predicted using default values into FDS and measured values in the present study were quantitatively compared. As a result, the Heskestad model could result in an inaccurate the activation time of photoelectric smoke detector compared to the Cleary model. In addition, there was a distinct difference between the default values used into FDS and the measured values in terms of device properties of smoke detector, and thus the activation time also showed a significant difference.

Measurement of the Device Properties of a Ionization Smoke Detector to Improve Predictive Performance of the Fire Modeling (화재모델링 예측성능 개선을 위한 이온화식 연기감지기의 장치물성 측정)

  • Kim, Kyung-Hwa;Hwang, Cheol-Hong
    • Fire Science and Engineering
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    • v.27 no.4
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    • pp.27-34
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    • 2013
  • The high prediction performance of fire detector models is essentially needed to assure the reliability of fire and evacuation modeling in the process of PBD (Performance Based fire safety Design). The main objective of the present study is to measure input information in order to predict the accurate activation time of smoke detector into a Large Eddy Simulation (LES) fire model such as FDS (Fire Dynamics Simulator). To end this, FDE (Fire Detector Evaluator) which can measure the device properties of detector was developed, and the input information of Heskestad and Cleary's models was measured for a ionization smoke detector. In addition, the activation times of smoke detectors predicted using default values into FDS and measured values in the present study were systematically compared. As a result, the device properties of smoke detector examined in the present study showed a significant difference compared to the default values used into FDS, which resulted in the considerable difference of up to 15 minutes or more in terms of the activation time of smoke detector. The database (DB) on device properties of various smoke and heat detectors will be built to improve the reliability of PBD in future studies.

High-Speed FPGA Implementation of SATA HDD Encryption Device based on Pipelined Architecture (고속 연산이 가능한 파이프라인 구조의 SATA HDD 암호화용 FPGA 설계 및 구현)

  • Koo, Bon-Seok;Lim, Jeong-Seok;Kim, Choon-Soo;Yoon, E-Joong;Lee, Sang-Jin
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.22 no.2
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    • pp.201-211
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    • 2012
  • This paper addresses a Full Disk Encryption hardware processor for SATA HDD in a single FPGA design, and shows its experimental result using an FPGA board. The proposed processor mainly consists of two blocks: the first block processes XTS-AES block cipher which is the IEEE P1619 standard of storage media encryption and the second block executes the interface between SATA Host (PC) and Device (HDD). To minimize the performance degradation, we designed the XTS-AES block with the 4-stage pipelined structure which can process a 128-bit block per 4 clock cycles and has 4.8Gbps (max) performance. Also, we implemented the proposed design with Xilinx ML507 FPGA board and our experiment showed 140MB/sec read/write speed in Windows XP 32-bit and a SATA II HDD. This performance is almost equivalent with the speed of the direct SATA connection without FDE devices, hence our proposed processor is very suitable for SATA HDD Full Disk Encryption environments.

Delay Determination for Cyclic Delay Diversity for Block-Hopping SC-FDMA Systems (블록호핑 SC-FDMA 시스템을 위한 순환지연 다이버시티의 지연값 결정)

  • Rim, Min-Joong
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.46 no.1
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    • pp.72-82
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    • 2009
  • In OFDMA systems, cyclic delay diversity can improve the system performance due to diversity effects. However, applying cyclic delay diversity to block-hopping SC-FDMA systems can affect the performance in two contrary ways: positive effect due to increased frequency diversity and negative effect caused by increased frequency selectivity. Hence, the delay value for cyclic delay diversity should be carefully selected to maximize the system performance. This paper discusses these two contrary effects and proposes a method of determining the delay value of cyclic delay diversity for block-hopping SC-FDMA systems.

Simplified approach for symbol error rate analysis of SC-FDMA scheme over Rayleigh fading channel

  • Trivedi, Vinay Kumar;Sinha, Madhusudan Kumar;Kumar, Preetam
    • ETRI Journal
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    • v.40 no.4
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    • pp.537-545
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    • 2018
  • In this paper, we present a comprehensive analytical study of the symbol error rate (SER) of single-carrier frequency-division multiple access (SC-FDMA) with zero-forcing frequency domain equalization (ZF-FDE) over a Rayleigh fading channel. SC-FDMA is considered as a potential waveform candidate for fifth-generation (5G) radio access networks (RANs). First, the $N_C$ fold convolution of the noise distribution of an orthogonal frequency-division multiplexing (OFDM) system is computed for each value of the signal-to-noise ratio (SNR) in order to determine the noise distribution of the SC-FDMA system. $N_C$ is the number of subcarriers assigned to a user or the size of the discrete Fourier transform (DFT) precoding. Here, we present a simple alternative method of calculating the SER by simplifying the $N_C$ fold convolution using time and amplitude scaling properties. The effects of the $N_C$ fold convolution and SNR over the computation of the SER of the SC-FDMA system has been separated out. As a result, the proposed approach only requires the computation of the $N_C$ fold convolution once, and it is used for different values of SNR to calculate the SER of SC-FDMA systems.

Multiple-Hypothesis RAIM Algorithm with an RRAIM Concept (RRAIM 기법을 활용한 다중 가설 사용자 무결성 감시 알고리듬)

  • Yun, Ho;Kee, Changdon
    • Journal of Advanced Navigation Technology
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    • v.16 no.4
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    • pp.593-601
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    • 2012
  • This paper develops and analyzes a new multiple-hypothesis Receiver Autonomous Integrity Monitoring (RAIM) algorithm as a candidate for future standard architecture. The proposed algorithm can handle simultaneous multiple failures as well as a single failure. It uses measurement residuals and satellite observation matrices of several consecutive epochs for Failure Detection and Exclusion (FDE). The proposed algorithm redueces the Minimum Detectable Bias (MDB) via the Relative RAIM (RRAIM) scheme. Simulation results show that the proposed algorithm can detect and filter out multiple failures in tens of meters.