• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.1
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• pp.51-58
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• 2011

Extensible processors provide an efficient mechanism to boost the performance of the whole system without losing much flexibility. However, due to the intense demand of low cost and power consumption, customizing an embedded system has been more difficult than ever. In this paper, we present a framework for custom instruction generation considering both area constraints and resource sharing. We also present how we can speed up the process through pruning and library-based design space exploration.

• KIPS Transactions on Computer and Communication Systems
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• v.11 no.1
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• pp.1-8
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• 2022

RISC-V is an open-source instruction set architecture which has a simple base structure and can be extensible depending on the purpose. In this paper, we designed a small and low-power 32-bit RISC-V processor to establish the base for research on RISC-V embedded systems. We designed a 2-stage pipelined processor which supports RISC-V base integer instruction set except for FENCE and EBREAK instructions. The processor also supports privileged ISA for trap handling. It used 1895 LUTs and 1195 flip-flops, and consumed 0.001W on Xilinx Zynq-7000 FPGA when synthesized using Vivado Design Suite. GPIO, UART, and timer peripherals are additionally used to compose the system. We verified the operation of the processor on FPGA with FreeRTOS at 16MHz. We used Dhrystone and Coremark benchmarks to measure the performance of the processor. This study aims to provide a low-power, high-efficiency microprocessor for future extension.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.33 no.1
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• pp.89-97
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• 2009

In this paper, a computer software for dynamic analysis of a high mobility tracked vehicle with pre/post processor is developed. Model of a tracked vehicle is composed of chassis, turret, mount, gun, and road-wheel assembly. Track is modeled as an extensible cable and the track tensions are applied on the wheels as external forces. The system equations of motion and constraint acceleration equations are derived in the joint coordinate space using the velocity transformation method. The pre and post processors are developed using the Visual C++.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.1
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• pp.239-245
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• 2019

RISC-V is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation. In this paper, according to the emergence of RISC-V architecture, we describe the RISC-V processor instruction set constituted by arithmetic logic, memory, branch, control, status register, environment call and break point instructions. Using ModelSim and Quartus-II, 38 instructions of RISC-V has been successfully simulated and synthesized.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.11
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• pp.1707-1712
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• 2013

In this paper, we implement a hardware for motor control based on FPGA + embedded processor using Zynq EPP which is All Programmable SoC in order to improve a structural problem of motion control based on such as DSP, MCU and FPGA previously. The implemented motor controller that is fused controller with advantage of FPGA and embedded processor. The signal processing part of high velocity motor control is performed by motor controller based on FPGA. A motion profile and kinematic calculation that are required algorithm process such as operation of a complicate decimal point has processed in an embedded processor based on dual core. As a result of a hardware implementation, it has an advantage that has can be realized an effect of distribution process in one chip. It has also an advantage that is able to organize as a multi-axis motor controller through adding the IP core of motor control implemented on FPGA.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.5 no.3
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• pp.241-246
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• 2004

We have designed LED display system using ARM7TDMI processor and implemented hangul input and output. This system is easily extensible because controller board and LED matrix board were designed one module. Possible Input Methods of LED display system are PC, PDA and remote controller's wired and wireless communication. We have ported QT/Embedded 2.3.7 with touch panel Input at embedded board of Linux OS 2.4.18 and PXA255 Processor based. QT Application which we coded is able to input displaying text using ethernet communication on embedded system. Many of indicating text data is able to be saved because only korean alphabet codes are stored for data which users want displaying.

• Proceedings of the Korean Information Science Society Conference
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• 2008.06b
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• pp.494-499
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• 2008

임베디드 시스템이 주목받으면서 개발상의 편의를 위해 시스템 시뮬레이터가 다양한 용도로 사용되고 있다. 시스템이 복잡해지고 소프트웨어의 규모가 커지면서 이러한 시스템 시뮬레이터들에 있어 그 성능은 매우 중요한 이슈가 되고 있는데, 본 논문에서는 공유 메모리를 사용하여 통신하는 다중 프로세서 시스템에서 동기화 횟수를 줄이는 방법을 제안하고 이를 기반으로 한 다중 프로세서 시스템 시뮬레이터를 개발하였다. 이 시뮬레이터는 프로세서 시뮬레이터의 내부를 크게 고치지 않고 공유 메모리 접근만을 가로채 동작이 가능하므로 쉽게 다양한 종류의 프로세서를 연결할 수 있는 확장성 역시 가지고 있다. 제안하는 동기화 기법과 개발된 시뮬레이터는 7개의 프로세서를 사용하여 동작하는 JPEG 인코더 예제의 구동을 통해 테스트되었으며, 이를 통해 인과율을 깨뜨리지 않고도 빠른 시뮬레이션이 가능함을 확인할 수 있었다.

• Proceedings of the Korea Information Processing Society Conference
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• 2019.05a
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• pp.335-338
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• 2019

북한에서 운영하고 있는 오피스 프로그램인 서광사무처리 3.0은 ODF(Open Document Format) 파일 포맷을 입력으로 받아 문서를 처리한다. ODF는 여러 개의 XML(Extensible Markup Language) 파일로 구성되어 있고, 하위 노드들을 통해서 파일 구조를 정의한다. 이러한 서광사무처리 3.0의 ODF 파일 구조를 하위 프로그램별 입력받는 파일 확장자에 따라 공통 영역과 가변 영역으로 비교하고, CVE(Common Vulnerabilities and Exposures)를 통해 ODF와 XML 주요 취약점을 분석한다.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.1
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• pp.68-80
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• 2000

The modern software technology toward modularization has changed the cache accessing behavior dramatically. Many modern operating systems are also departing from the past monolithic structure toward the highly modularized structure referred to as microkernel. Microkernel-based operating systems are more portable and extensible, but are likely to have worse performance. This paper quantitatively analyzes the effect of microkernel structure on cache memory to identify the primary factor for its performance degradation. Through the experiment performed on a Intel Pentium Pro processor platform, we found that the microkernel structure suffers from remarkably higher misses for L1, L2 cache and TLB than the monolithic one does. We also found that the performance of a microkernel is more dependent on the efficiency of cache memory than IPC. Finally, we found that these results come from the effect of frequent context switches mainly caused by the structural feature of a microkernel.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.38 no.3
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• pp.217-227
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• 1989

A process control graphic system is proposed as an efficient tool for monitoring the operation of power plant. It uses the multi-processor structure with 60 Kbyte shared memory as an implemental type of the distributed computer system, so that it is flexible, functionally extensible, and applicable to real-time process. The shared memory is used as a real-time database handling the process values and operator's commands. The database files, generated by the user-interactive graphic editor developed for the system or text editor, have the characteristics of simplicity and user-friendliness. The process control graphic system, that can monitor the operation of boiler and function as a backup controller in case of failure in boiler controller, is applied to Ulsan power plant. As a result, it displays the operating data of the boiler process without error by 14 pages of color graphic image according to the operation menu, and additionally functions well as a fault-tolerant control system.