• Journal of KIISE:Computer Systems and Theory
• /
• v.30 no.3_4
• /
• pp.186-193
• /
• 2003

In recent years the complexity of digital systems has increased dramatically. Although semiconductor manufacturers try to ensure that their products are reliable, it is almost impossible not to have faults somewhere in a system at any given time. As complexity of circuits increases, the necessity of more efficient organized and automated methods for test generation is growing. But, up to now, most of popular and extensive methods for test generation nay be those which sequentially produce an output for an input pattern. They inevitably require a lot of time to search each fault in a system. In this paper, corresponding test patterns are generated through the partitioning method among those based on the exhaustive method. In addition, the method, which can discovers faults faster than other ones that have been proposed ever by inserting a pattern in parallel, is designed and implemented.

• The Transactions of the Korea Information Processing Society
• /
• v.1 no.2
• /
• pp.272-278
• /
• 1994

The paper proposes a test pattern generator and a signature analyzer for pseudoexhaustive testing of the combinational circuit part within a sequential circuit when performing built-in self test of the circuit. The test pattern generator can scan in the seed test pattern and generate exhaustive test patterns. The signature analyzer can perform the analysis of the circuit response and scan out the result. Such test pattern generator and signature analyzer have been developed using SRL(shift register latch) and LFSR(linear feedback shift register).

• Journal of the Korea Computer Industry Society
• /
• v.6 no.2
• /
• pp.295-304
• /
• 2005

This paper presents the problem of exhaustive test generation for detection of coupling faults between cells in word-oriented memories. According to this fault model, contents of any w-bit memory word in a memory with n words, or ability tochange this contents, is influenced by the contents of any other s-1 words in the memory. A near optimal iterative method for construction of test patterns is proposed The systematic structure of the proposed test results in simple BIST implementations.

• Transactions of the Korean Society of Mechanical Engineers
• /
• v.18 no.10
• /
• pp.2606-2615
• /
• 1994

Sorting time is one of the most important issues for auto IC test handling systems. In actual system, because of too much path, reducing the computing time for finding a sorting path is the key way to enhancing the system performance. The exhaustive path search technique can not be used for real systems. This paper proposes heuristic sorting algorithm to find the minimal sorting time. The suggested algorithm is basically based on the best-first search technique and multi-level search technique. The results are close to the optimal solutions and computing time is greately reduced also. Therefore the proposed algorthm can be effectively used for real-time sorting process in auto IC test handling systems.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.8 no.6
• /
• pp.1458-1464
• /
• 2007

Today, domestic and foreign manufacturing industries have to cope with obsolescence of manufacturing equipment because the shifting market trends drive the rapid changes in the production process resulting in stressful operation. Quality control process for manufacturing and production involves a familiar step - when the production process is completed, every item is subjected to various routine tests to determine that it meets the minimum quality standards. Typically, when a faulty product is found, the production line has to be stopped and the current batch is marked for further inspected and exhaustive testing. In this research, we propose a quality monitoring system for productivity enhancement. Our approach aims to reduces the operational down time in the production line of a car-component factory. The proposed monitoring system for productivity enhancement is designed to collect the data through testing at each phase of the assembly line and uses predictive methods on the collected data to achieve early detection of faults in the production process and minimize the number of products in a faulty batch thus minimizing the losses incurred from defective products. More importantly, this system aims to forecast and proactively detect faults and activate warnings when they are detected thus minimizing items in the defective batch, reducing the damage to manufacturing equipment and ultimately reducing the operational downtime or the delay in the resumption of normal factory operation.

• The KIPS Transactions:PartD
• /
• v.16D no.3
• /
• pp.295-306
• /
• 2009

Query execution time minimization is an important objective in distributed database design. While total time minimization is an objective for On Line Transaction Processing (OLTP), response time minimization is for Decision Support queries. We formulate the sub-query allocation problem using analytical models and solve with genetic algorithm (GA). We show that query execution plans with total time minimization objective are inefficient from response time perspective and vice versa. The procedure is tested with simulation experiments for queries of up to 20 joins. Comparison with exhaustive enumeration indicates that GA produced optimal solutions in all cases in much less time.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.53 no.7
• /
• pp.49-55
• /
• 2016

In digital forensic images, there is a serious problem that is distributed with various image types. For the problem solution, this paper proposes a classification algorithm of the forensic image types. The proposed algorithm extracts the 21-dim. feature vector with the contrast and energy from GLCM (Gray Level Co-occurrence Matrix), and the entropy of each image type. The classification test of the forensic images is performed with an exhaustive combination of the image types. Through the experiments, TP (True Positive) and FN (False Negative) is detected respectively. While it is confirmed that performed class evaluation of the proposed algorithm is rated as 'Excellent(A)' because of the AUROC (Area Under Receiver Operating Characteristic Curve) is 0.9980 by the sensitivity and the 1-specificity. Also, the minimum average decision error is 0.1349. Also, at the minimum average decision error is 0.0179, the whole forensic image types which are involved then, our classification effectiveness is high.

• The Transactions of the Korean Institute of Electrical Engineers D
• /
• v.49 no.6
• /
• pp.322-329
• /
• 2000

BIST(Built-in Self Test) has been considered as the most promising DFT(design-for-test) scheme for the present and future test strategy. The most serious problem in applying BIST(Built-in Self Test) into a large circuit is the excessive increase in test time. This paper is focused on this problem. We proposed a new BIST construction scheme which uses a parallel divide-and-conquer method. The circuit division is performed with respect to some internal nodes called test points. The test points are selected by considering the nodal connectivity of the circuit rather than the testability of each node. The test patterns are generated by only one linear feedback shift register(LFSR) and they are shared by all the divided circuits. Thus, the test for each divided circuit is performed in parallel. Test responses are collected from the test point as well as the primary outputs. Even though the divide-and-conquer scheme is used and test patterns are generated in one LFSR, the proposed scheme does not lose its pseudo-exhaustive property. We proposed a selection procedure to find the test points and it was implemented with C/C++ language. Several example circuits were applied to this procedure and the results showed that test time was reduced upto 1/2151 but the increase in the hardware overhead or the delay increase was not much high. Because the proposed scheme showed a tendency that the increasing rates in hardware overhead and delay overhead were less than that in test time reduction as the size of circuit increases, it is expected to be used efficiently for large circuits as VLSI and ULSI.