• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.3
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• pp.62-70
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• 2011

Nowadays image sensor is an essential component in many multimedia devices, and it is covered by a color filter array to filter out specific color components at each pixel. We need a certain algorithm to combine those color components reconstructed a full color image from incomplete color samples output from an image sensor, which is called a demosaicking process. Most existing demosaicking algorithms are developed for ideal image sensors, but they do not work well for the practical cases because of dissimilar characteristics of each sensor. In this paper, we propose a new demosaicking algorithm in which the color filter characteristics are fully utilized to generate a good image. To demonstrate significance of our algorithm, we used a commerically available sensor, CBN385B, which is a sort of Honeycomb-style CFA(Color Filter Array) CCD image sensor. As a performance metric of the algorithm, PSNR(Peak Signal to Noise Ratio) and RGB distribution of the output image are used. We first implemented our algorithm in C-language for simulation on various input images. As a result, we could obtain much enhanced images whose PSNR was improved by 4~8 dB compared to the commonly idealized approaches, and we also could remove the inclined red property which was an unique characteristics of the image sensor(CBN385B).Then we implemented it in hardware to overcome its problem of computational complexity which made it operate slow in software. The hardware was verified on Spartan-3E FPGA(Field Programable Gate Array) to give almost the same performance as software, but in much faster execution time. The total logic gate count is 45K, and it handles 25 image frmaes per second.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.10a
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• pp.497-500
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• 2010

Wireless sensor network is the system for data collection and data process between many nodes. For this work, Synchronization of operation execution and ordering many events are needed. Reference the external time information is the most accurate way to have same time information for all nodes but it's hard to apply these to sensor network. So there are many study of time synchronization there are many error occurred when the time synchronization is executed in the sensor network and minimizing these errors is important. In this paper, we propose how to minimize errors using several time stamp information exchanging when the network is initialized. When the big difference is occurred between receive time and send time in the node communication(cause of traffic overhead and etc), it shows big error of time correction and transfer delay time. but it's hard to detect these errors when it exchanges time stamp information just one time. so we try to reduce these errors using the median value of transfer delay and time correction value with many times of time stamp information exchange.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.45 no.1
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• pp.41-49
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• 2008

Many machineries and equipments are being changing to various and complicated by development of recent technology and arrival of convergence age in distant future. These various and complicate equipments need more precise outcomes and low-power consumption sensors to get close and exact results. In this paper, we proposed fault tolerance and feedback theorem for sensor network and MEMS circuit which has a benefit of energy efficiency through wireless sensor network. The system is provided with independent sensor communication if possible as unused action, using idle condition of system and is proposed the least number of circuits. These technologies compared system efficiency after examining product of each Moving Distance by developed sensor which gives effects to execution of system witch is reduced things like control of management side and requirement for hardware, time, and interaction problems. This system is designed for practical application; however, it can be applied to a normal life and production environment such as "Ubiquitous City", "Factory Automata ion Process", and "Real-time Operating System", etc.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.10
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• pp.82-90
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• 2011

Because of the development of Smart phone devices, the demands of high performance FPU(Floating-point Unit) becomes increasing. Therefore, we propose the high-speed single-/double-precision FPU design that includes an elementary add/sub unit and improved multiplier and compare and convert units. The most commonly used add/sub unit is optimized by the parallel rounding unit. The matrix operation is used in complex calculation something like a graphic calculation. We designed the Multiply-Add Fused(MAF) instead of multiplier to calculate the matrix more quickly. The branch instruction that is decided by the compare operation is very frequently used in various programs. We bypassed the result of the compare operation before all the pipeline processes ended to decrease the total execution time. And we included additional convert operations that are added in IEEE754-2008 standard. To verify our RTL designs, we chose four hundred thousand test vectors by weighted random method and simulated each unit. The FPU that was synthesized by Samsung's 45-nm low-power process satisfied the 600-MHz operation frequency. And we confirm a reduction in area by comparing the improved FPU with the existing FPU.

• Journal of Environmental Policy
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• v.10 no.1
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• pp.129-150
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• 2011

This paper proposes an improvement to differentiate assessment procedure for projects in consideration of their environmental impact as a means to improve efficiency in environmental impact assessment ("EIA") procedure. The targets of analysis were limited to lower impact projects. The current EA system in Korea has already attempted to introduce separate proceedings for certain projects.Tangible results from these efforts, however, have been limited. Other countries have adopted a "screening" system to determine whether EIA is applicable to a particular project, and if so, what procedure will be used therein. Therefore, this study suggests the screening as the process wherein need for EIA is determined with respect to projects which have undergone Prior Environmental Review System(PERS) and which appear to have comparatively negligible environmental impact. In this case, EIA can be omitted and the developer can then draft a mitigation plan instead. This study found that exempting certain projects deemed as having low environmental impact can considerably shorten the duration required for both environmental assessment and consultation, thereby improving efficiency. Other expected effects from the adoption of this screening include reduction in delays in project execution due to environmental assessments and reduced red tape through the provision of increased autonomy to developers and the approving authorities.

• Korean Chemical Engineering Research
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• v.58 no.2
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• pp.209-223
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• 2020

Executions of SCM in a chemical company of which divisions produce petrochemicals, compounds, batteries, IT material and medicine directly affect their own profit. Execution level of SCM or optimization is very important. This work presents activities of SCM and optimization of inefficient issues in several industrial divisions using mathematical optimization method. The meaning is not only academic research but also making a useful tool which active partner deals with in his work. It is explained how to do beforehand and afterward optimization problem. The benefits are mentioned in the sections. The first of examples would be cover supply plan optimization, optimal profit business plan, and scheduling of a stretching process of polarizer based on minimizing raw material loss in polarizer production. The second example would be cover the optimization of production/packaging plans to maximize productivity of Poly Olefin processes, and the third example is minimization of transition loss in the production of battery electrodes. The fourth example would be cover scheduling of vessel approaching to berth. Because transportation of large portion of raw material and products of petrochemical industry is dealt with vessel, scheduling of vessel approaching to berth is important at the shore of large difference of tide. The final example would be scheduling problem to minimization of change over time of ABS semi products.

• Journal of KIISE
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• v.42 no.4
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• pp.434-441
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• 2015

Next generation memory technologies, which we denote as 'new memory', have both non-volatile and byte addressable properties. These characteristics are expected to bring changes to the conventional computer system structure. In this paper, we propose a fast boot technique for hybrid main memory architectures that have both new memory and DRAM. The key technique used for fast booting is write-tracking. Write-tracking is used to detect and manage modified data detection and involves setting the kernel region to read-only. This setting is used to trigger intentional faults upon modification requests. As the fault handler can detect the faulting address, write-tracking makes use of the address to manage the modified data. In particular, in our case, we make use of the MMU (Memory Management Unit) translation table. When a write occurs to the boot completed state, write-tracking preserves the original state of the modified address of the kernel region to a particular location, and execution continues. Upon booting, the fast booting process restores the preserved data to the original kernel region allowing rapid system boot-up. We develop the fast booting technique in an actual embedded board equipped with new memory. The boot time is reduced to less than half a second compared to around 15 seconds that is required for the original system.

• The KIPS Transactions:PartA
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• v.17A no.6
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• pp.265-274
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• 2010

As the process technology scales down and integration densities continue to increase, interconnection has become one of the most important factors in performance of recent multi-core processors. Recently, to reduce the delay due to interconnection, 3D architecture has been adopted in designing multi-core processors. In 3D multi-core processors, multiple cores are stacked vertically and each core on different layers are connected by direct vertical TSVs(through-silicon vias). Compared to 2D multi-core architecture, 3D multi-core architecture reduces wire length significantly, leading to decreased interconnection delay and lower power consumption. Despite the benefits mentioned above, 3D design technique cannot be practical without proper solutions for hotspots due to high temperature. In this paper, we propose three floorplan schemes for reducing the peak temperature in 3D multi-core processors. According to our simulation results, the proposed floorplan schemes are expected to mitigate the thermal problems of 3D multi-core processors efficiently, resulting in improved reliability. Moreover, processor performance improves by reducing the performance degradation due to DTM techniques. Power consumption also can be reduced by decreased temperature and reduced execution time.

• Journal of KIISE:Computer Systems and Theory
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• v.37 no.3
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• pp.172-183
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• 2010

Virtual memory systems (VM) reduce disk I/Os caused by page faults using page prefetching, which reads pages together with a desired page at a page fault in a single disk I/O. Operating systems including 4.4BSD attempt to prefetch as many pages as possible at a page fault regardless of page access patterns of applications. However, such an approach increases a disk access time taken to service a page fault when a high portion of the prefetched pages is not referenced. More seriously, the approach can cause the memory pollution, a problem that prefetched pages not to be accessed evict another pages that will be referenced soon. To solve these problems, we propose an adaptive page prefetching control scheme (APC), which periodically monitors access patterns of prefetched pages in a process unit. Such a pattern is represented as the ratio of referenced pages among prefetched ones before they are evicted from memory. Then APC uses the ratio to adjust the number of pages that 4.4BSD VM intends to prefetch at a page fault. Thus APC allows 4.4BSD VM to prefetch a proper number of pages to have a better effect on reducing disk I/Os, though page access patterns of an application vary in runtime. The experiment of our technique implemented in FreeBSD 6.2 shows that APC improves the execution times of SOR, SMM, and FFT benchmarks over 4.4BSD VM by up to 57%.

• Journal of KIISE:Databases
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• v.35 no.6
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• pp.459-468
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• 2008

A data stream which is a massive unbounded sequence of data elements continuously generated at a rapid rate. Many recent research activities for emerging applications often need to deal with the data stream. Such applications can be web click monitoring, sensor data processing, network traffic analysis. telephone records and multi-media data. For this. data processing over a data stream are not performed on the stored data but performed the newly updated data with pre-registered queries, and then return a result immediately or periodically. Recently, many studies are focused on dealing with a data stream more than a stored data set. Especially. there are many researches to optimize continuous queries in order to perform them efficiently. This paper proposes a query optimization algorithm to manage continuous query which has multiple join operators(Multi-way join) over data streams. It is called by an Extended Greedy query optimization based on a greedy algorithm. It defines a join cost by a required operation to compute a join and an operation to process a result and then stores all information for computing join cost and join cost in the statistics catalog. To overcome a weak point of greedy algorithm which has poor performance, the algorithm selects the set of operators with a small lay, instead of operator with the smallest cost. The set is influenced the accuracy and execution time of the algorithm and can be controlled adaptively by two user-defined values. Experiment results illustrate the performance of the EGA algorithm in various stream environments.