• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.1355-1360
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• 2005

In this paper, we approach the problem of image filter design automation using a kind of intrinsic evolvable hardware architecture. For the purpose of implementing the intrinsic evolution process in a common FPGA chip and evolving a complicated digital circuit system-image filter, the design automation system employs the reconfigurable circuit architecture as the reconfigurable component of the EHW. The reconfigurable circuit architecture is inspired by the Cartesian Genetic Programming and the functional level evolution. To increase the speed of the hardware evolution, the whole evolvable hardware system which consists of evolution algorithm unit, fitness value calculation unit and reconfigurable unit are implemented by a commercial FPGA chip. The Celoxica RC1000 card which is fitted with a Xilinx Virtex xcv2000E FPGA chip is employed as the experiment platform. As the result, we conclude the terms of the synthesis report of the image filter design automation system and hardware evolution speed in the Celoxica RC1000 card. The evolved image filter is also compared with the conventional image filter form the point of filtered image quality.

• 제어로봇시스템학회:학술대회논문집
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• 2002.10a
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• pp.102.6-102
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• 2002

$\textbullet$ Introduction $\textbullet$ Background - Handel-C and Evolvable Hardware $\textbullet$ Fitter Block $\textbullet$ Hardware Implementation $\textbullet$ Total System Overview $\textbullet$ Results $\textbullet$ Conclusion and Future Works

• The Journal of the Korea Contents Association
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• v.9 no.6
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• pp.1-8
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• 2009

There are a lot of influences, such as location of camera, luminosity, brightness, and direction of light, which affect the performance of 2-dimensional image recognition. This paper suggests an adaptive method for face-image recognition in noisy environments using evolvable filtering and feature extraction which uses one sample image from camera. This suggested method consists of two main parts. One is the environmental-adjustment module which determines optimum sets of filters, filter parameters, and dimensions of features by using "steady state genetic algorithm". The other another part is for face recognition module which performs recognition of face-image using the previous results. In the processing, we used Gabor wavelet for extracting features in the images and k-Nearest Neighbor method for the classification. For testing of the adaptive face recognition method, we tested the adaptive method in the brightness noise, in the impulse noise and in the composite noise and verified that the adaptive method protects face recognition-rate's rapidly decrease which can be occurred generally in the noisy environments.

• Proceedings of the KIEE Conference
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• 2002.07d
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• pp.2783-2787
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• 2002

최근 멀티미디어 및 통신의 발달로 인하여 영상 정보를 이용한 응용시스템이 많이 연구되고있다. 중간 전달 매체를 이용한 응용시스템으로의 영상 정보를 전달과정에서 잡영(noise) 이 포함되어 시스템의 성능을 저하시키게 된다. 또한 잡영은 임의의 형태이기 때문에 상황에 따라 적합한 필터를 선택하기는 쉽지 않다. 본 논문에서는 유전자 알고리즘 프로세서를 이용하여 필터들의 구성 및 파라미터를 조절하여 임의의 잡영에 진화적응적인 능력을 가지는 영상 전처리 필터를 구현하였다. 주파수 영역의 잡영에 대해서는 하드웨어에 적합하고 구현이 용이한 멀티밴드필터(Multi-Band filter)를 설계하여 사용하였다. 시스템은 유전자알고리즘과 필터블록에 대해서는 하드웨어(FPCA)로 구현하였고 적합도 평가는 PC 기반으로 수행하였다. 실험결과 순수 PC기반의 시뮬레이션에 비해 속도향상 및 성능면에서도 만족할 만한 결과를 얻었다.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.663-664
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• 2006

This paper presents a reconfigurable digital signal processing(rDSP) architecture that is effective for implementing adaptive digital signal processing in the applications of smart health care system. This rDSP architecture employs an evolution capability of FIR filters using genetic algorithm. Parallel genetic algorithm based rDSP architecture evolves FIR filters to explore optimal configuration of filter combination, associated parameters, and structure of feature space adaptively to noisy environments for an adaptive signal processing. The proposed DSP architecture is implemented using Xilinx Virtex4 FPGA device and SMIC 0.18um CMOS Technology.