• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.255-258
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• 2000

This paper presents an Interprocessor Communication Network(IPC net) in ATM switching system. In order to supply stable and independent path for processor communication, additional network i.e., Ethernet, is suggested. An Ethernet switch centered on Ethernet binds each processor into a work range. IPC net proposed in this paper assures end-to-end inter-processor connection, uniform 100Mbps Ethernet bandwidth and enhanced user cell throughput of ATM switch with minimum Ethernet supporting block integrated into ATM system

• Journal of Communications and Networks
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• v.17 no.3
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• pp.286-295
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• 2015

Avionic databuses fulfill a critical function in the connection and communication of aircraft components and functions such as flight-control, navigation, and monitoring. Ethernet-based avionic databuses have become the mainstream for large aircraft owning to their advantages of full-duplex communication with high bandwidth, low latency, low packet-loss, and low cost. As a new generation aviation network communication standard, avionics full-duplex switched ethernet (AFDX) adopted concepts from the telecom standard, asynchronous transfer mode (ATM). In this technology, the switches are the key devices influencing the overall performance. This paper reviews the avionic databus with emphasis on the switch architecture classifications. Based on a comparison, analysis, and discussion of the different switch architectures, we propose a new avionic switch design based on a time-division switch fabric for high flexibility and scalability. This also merges the design concept of space-partition switch fabric to achieve reliability and predictability. The new switch architecture, called space partitioned shared memory switch (SPSMS), isolates the memory space for each output port. This can reduce the competition for resources and avoid conflicts, decrease the packet forwarding latency through the switch, and reduce the packet loss rate. A simulation of the architecture with optimized network engineering tools (OPNET) confirms the efficiency and significant performance improvement over a classic shared memory switch, in terms of overall packet latency, queuing delay, and queue size.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.441-444
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• 2000

This paper covers the performance testing for layer 3 Ethernet switch based on various methodologies by which we can measure essential metrics such as throughput, latency, frame loss rate, and back to back frames. In the first place, layer 2 and layer 3 switch evolution is introduced followed by description of IP packet switching in layer 3 switch. And then, the above test metrics and test methodologies are illustrated as well. At last, we conduct the performance testing for layer 3 switch in case of transmitting packets of 64, 128, 256, 512, 1024, 1280, and 1518 byte size and analyze then results.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.5
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• pp.27-36
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• 2004

In this paper, we propose the ethernet Inter-Processor Communication (IPC) network architecture and 10gigabit ethernet frame multiplex/demultiplexer architecture for the edge switch system based on Linux that has 10 Gigabit Ethernet (10Gigabit Ethernet) port with 72Gbps capacities. we discuss the ethernet IPC with ethernet switch and we propose design and implementation of ethernet Inter-Processor Communication (IPC) network architecture and multiple gigabit ethernet frame rnultiplexing/demultiplexing scheme to handle 10gigabit ethernet frame instead of using 10gigabit network processor. And then ethernet Inter-Processor Communication (IPC) network architecture and 10gigabit ethernet frame MUX/DMUX architecture is designed verified and implemented.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.3
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• pp.389-395
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• 2013

Ethernet is the most widely deployed access network protocol around the world. IEEE 802.3az WG released the EEE standard based on LPI mode to improve the energy efficiency of Ethernet. This paper proposes improved adaptive power control mechanism that can enhance energy-efficiency based on EEE from small Ethernet switch. The feature of this mechanism is that it predicts the traffic characteristic of next cycle by measuring the amount of traffic flowing in during certain period and adjusts the optimal threshold value to relevant traffic load. Performance evaluation results indicate that the proposed mechanism improves overall performance compared to traditional mechanism, since it significantly reduces energy consumption rate, even though average packet delay increases a little bit.

• TTA Journal
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• s.87
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• pp.157-161
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• 2003

한국정보통신기술협회(TTA)는 2003년 3월 7일 대은전자㈜(http://www.dek.co.kr/) Gate Hub(모델명: DEK1521)의 성능시험을 수행하여 TTA Verified 인증서(번호: TTA-V-N-03-014)를 발급하였다. 또한 2003년 4월 3일 ㈜네오정보시스템(http://www.neoinfosys.co.kr/) 세대통신 분배장치(모델명: NIS - HM1616A)의 성능시험을 수행하여 TTA Verified 인증서(번호: TTA-V-N-03-026)를 발급하였다. 위의 두 장비는 Fast Ethernet Switch module과 전화 및 데이터 라인 연결 module을 함께 갖추었으며, TTA가 위의 두 장비를 이용하여 수행한 시험은 Fast Ethernet Switch module의 성능을 측정하는 것이었다. 본 고에서는 TTA가 마련한 Fast Ethernet Switch에 대한 인증기준(TTA-V-N-03-004-CC20)을 바탕으로 위의 두 장비에 대해 수행한 Fully meshed Throughput/Aging 시험 결과를 소개한다.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.799-802
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• 1998

As we know, gigabit ethernet is a new technology to be substituted for current fast ethernet used widely in local area network. The switch used in gigabit ethernet should deal with frames in giga-bps. To do such a fast switching, we need that serveral processes meet the budgets, such as MAC address table lookup, several giga speed path setup, fast scheduling, and etc. Especially MAC address table lookup has to be processed in the same speed with speed of incoming packets, thus the bottleneck in the process can cause packet loss by the overflow in the input buffer. We devise new practical hardware hashing method to perform fast table lookup by minimizing the number of external memory access and accelerating with hardware.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.48 no.4
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• pp.71-79
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• 2011

This paper proposes a reliability enhancement of industrial real-time Ethernet using master redundancy method for NPPs(Nuclear Power Plants). In this paper, Ethernet Powerlink is investigated for distributed control systems for NPPs considering real-time and reliability performance. The proposed method can reduce a master switch-over time using PReq signal when Ethernet Powerlink master(Managing Node) failure was occurred. Using the OPNET simulation results, the performance enhancement of master switch-over time of Ethernet Powerlink is verified for NPPs.

• Journal of Communications and Networks
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• v.8 no.4
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• pp.480-484
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• 2006

This paper briefly reviews ITU-T recommendations associated with multi protocol label switch (MPLS) and Ethernet operation, administration, and maintenance (OAM). The broadband convergence network (BcN) architecture with a centralized network controller is introduced. An aggregation structure employing Ethernet, MPLS, and time division multiplexing (TDM) signal is presented for the BcN. A physical link failure scenario is examined to investigate how the maintenance signal is propagated between different layers.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.209-212
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• 2000

This paper discusses performance evaluation methodologies for wired/wireless Ethernet adaptors. This paper defines test cases for performance evaluation of LAN adaptor and its environments. Performance evaluation of LAN adaptor is mote complex as compared with interconnection devices such as Ethernet HUB and Ethernet switch, because its performance depends on the system on which the adaptor is plugged. Such dependencies include CUP type, RAM size, system bus architecture(PCI bus clock), etc.