• The Transactions of the Korean Institute of Electrical Engineers C
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• v.51 no.4
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• pp.147-151
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• 2002

The resistances of metal2 contact to metall and poly Si are checked by various RF etch conditions in terms of pre-cleaning. The changes of resistance are evaluated by statistical analysis method(SAS) for the AC bias power, coil power and RF target. The contact area on poly Si is shown by TEM image and the distributions of contact resistance according to ar etch target and RTP are investigated. The RTP groups have larger variations than normal RF etch targets. When the RF etch target becomes lower and coil power becomes higher, the resistances of metal2 contact to metals and poly Si have lower contact resistance. But the condition of AC bias power did not satisfied low meta12 contacts resistance for metall and poly Si simultaneously. The R-square of ststistical analysis was 0.98 for resistances of meta12 contact to poly Si and 0.87 for resistances of meta12 contact to metall.

• Journal of the Korean Ceramic Society
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• v.49 no.4
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• pp.328-332
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• 2012

Etch rates of Si and high purity SiC have been compared for various fluorocarbon plasmas. The relative plasma resistance of SiC, which is defined as the etch rate ratio of Si to SiC, varied between 1.4 and 4.1, showing generally higher plasma resistance of SiC. High resolution X-ray photoelectron analysis revealed that etched SiC has a surface carbon content higher than that of etched Si, resulting in a thicker fluorocarbon polymer layer on the SiC surface. The plasma resistance of SiC was correlated with this thick fluorocarbon polymer layer, which reduced the reaction probability of fluorine-containing species in the plasma with silicon from the SiC substrate. The remnant carbon after the removal of Si as volatile etch products augments the surface carbon, and seems to be the origin of the higher plasma resistance of SiC.

• New & Renewable Energy
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• v.4 no.2
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• pp.74-80
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• 2008

To improve the blue responses of screen-printed single crystalline silicon solar cells, we investigated an emitter etch-back technique to obtain high emitter sheet resistances, where the defective dead layer on the emitter surface was etched and became thinner as the etch-back time increased, resulting in the monotonous increase of short circuit current and open circuit voltage. We found that an optimal etch-back time should be determined to achieve the maximal performance enhancement because of fill factor decrease due to a series resistance increment mainly affected by contact and lateral resistance in this case. To elucidate the reason for the fill factor decrease, we studied the resistance analysis by potential mapping to determine the contact and the lateral series resistance. As a result, we found that the fill factor decrease was attributed to the relatively fast increase of contact resistance due to the dead layer thinning down with the lowest contact resistivity when the emitter was contacted with screen-printed silver electrode.

• 한국신재생에너지학회:학술대회논문집
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• 2008.05a
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• pp.390-393
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• 2008

To improve the blue responses of screen-printed single crystalline silicon solar cells, we investigated an emitter etch-back technique to obtain high emitter sheet resistances, where the defective dead layer on the emitter surface was etched and became thinner as the etch-back time increased, resulting in the monotonous increase of short circuit current and open circuit voltage. We found that an optimal etch-back time should be determined to achieve the maximal performance enhancement because of fill factor decrease due to a series resistance increment mainly affected by contact and lateral resistance in this case. To elucidate the reason for the fill factor decrease, we studied the resistance analysis by potential mapping to determine the contact and the lateral series resistance. As a result, we found that the fill factor decrease was attributed to the relatively fast increase of contact resistance due to the dead layer thinning down with the lowest contact resistivity when the emitter was contacted with screen-printed silver electrode.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.9
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• pp.551-554
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• 2014

This paper was showed latch up characteristics of super junction power MOSFET by parasitic thyristor according to trench etch angle. As a result of research, if trench etch angle of super junction MOSFET is larger, we obtained large latch up voltage. When trench etch angle was $90^{\circ}$, latch up voltage was more 50 V. and we got 700 V breakdown voltage. But we analyzed on resistance. if trench etch angle of super junction MOSFET is larger, we obtained high on resistance. Therefore, we need optimal point by simulation and experiment for solution of trade off.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.10a
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• pp.268-271
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• 2005

Etch resistance of mask layer on silicon substrate modified by AFM-based Tribo-Nanolithography (TNL) in Aqueous Solution in an aqueous solution was demonstrated. n consists or sequential processes, nano-scratching and wet chemical etching. The simple scratching can form a mask layer on the silicon substrate, which acting as an etching mask. For TNL, a specially designed cantilever with diamond tip, allowing the formation of mask layer on silicon substrate easily by a simple scratching process, has been applied instead of conventional silicon cantilever fur scanning. This study demonstrates how the TNL parameters can affect the etch resistance of mask layer, hence introducing a new process of AFM-based maskless nanolithography in aqueous solution.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2007.11a
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• pp.155-156
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• 2007

• Journal of IKEEE
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• v.18 no.4
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• pp.532-535
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• 2014

This paper analyzed thermal characteristics of super junction MOSFET using process and design parameters. Trench process is very important to super junction MOSFET process. We analyzed the difference of temperature, thermal resistance, total power consumption according to trench etch angle. As a result we obtained minimum value of temperature difference and thermal resistance at $89.3^{\circ}$ of trench etch angle. The electrical characteristics distribution of super junction MOSFET is not showed tendency according to trench etch angle. We need iterative experiments and simulation for optimal value of electrical characteristics. The super junction power MOSFET that has superior thermal characteristics will use automobile and industry.

• Journal of the Korean Ceramic Society
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• v.53 no.6
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• pp.700-706
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• 2016

Etch rate, surface roughness and microstructure as plasma resistance were evaluated for six kinds of oxide glass with different compositions. Borosilicate glass (BS) was found to be etched at the highest etch rate and zinc aluminum phosphate glass (ZAP) showed a relatively lower etch rate than borosilicate. On the other hand, the etching rate of calcium aluminosilicate glass (CAS) was measured to be similar to that of sintered alumina while yttrium aluminosilicate glass (YAS) showed the lowest etch rate. Such different etch rates by mixture plasma as a function of glass compositions was dependent on whether or not fluoride compounds were formed on glass and sublimated in high vacuum. Especially, in view that $CaF_2$ and $YF_3$ with high sublimation points were formed on the surface of CAS and YAS glasses, both CAS and YAS glasses were considered to be a good candidate for protective coating materials on the damaged polycrystalline ceramics parts in semi-conductor and display processes.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2003.05a
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• pp.41-41
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• 2003

텅스텐(W)은 높은 thermal stability 와 process compatibility 및 우수한 corrosion r resistance 둥으로 integrated circuit (IC)의 gate 및 interconnection 둥으로의 활용이 대두되고 있으며, 차세대 thin film transistor liquid crystal display (TFT-LCD)의 gate 및 interconnection m materials 둥으로 사용되고 았다. 그러나, 이러한 장점을 가지고 있는 팅스텐 박막이 실제 공정상에 적용되가 위해서는 건식 식각이 주로 사용되는데, 이는 wet chemical 을 이용한 습식 식각을 사용할 경우 낮은 etch rate, line width 의 감소 및 postetch residue 잔류 동의 문제가 발생하기 때문이다. 또한 W interconnection etching 을 하기 위해서는 높은 텅스텐 박막의 etch rate 과 하부 layer ( (amorphous silicon 또는 poly-SD와의 높은 etch selectivity 가 필수적 이 라 할 수 있다. 그러 나, 지금까지 연구되어온 결과에 따르면 텅스탠과 하부 layer 와의 etch selectivity 는 2 이하로 매우 낮게 관찰되고 았으며, 텅스텐의 etch rate 또한 150nm/min 이하로 낮은 값을 나타내고 있다. 따라서 본 연구에서는 halogen-based inductively coupled plasma 를 이용하여 텅스텐 박막 식각시 여러 가지 첨가 가스에 따른 높은 텅스탠 박막의 etch rate 과 하부 layer 와의 높은 etch s selectivity 를 얻고자 하였으며, 그에 따른 식각 메커니즘에 대하여 알아보고자 하였다. $CF_4/Cl_2$ gas chemistry 에 첨 가 가스로 $N_2$와 Ar을 첨 가할 경 우 텅 스텐 박막과 하부 layer 간의 etch selectivity 증가는 관찰되지 않았으며, 반면에 첨가 가스로 $O_2$를 사용할 경우, $O_2$의 첨가량이 증가함에 따라 etch s selectivity 는 계속적으로 증가렴을 관찰할 수 있었다. 이는 $O_2$ 첨가에 따라 형성되는 WOF4 에 의한 텅스텐의 etch rates 의 감소에 비하여, $Si0_2$ 등의 형성에 의한 poly-Si etch rates 이 더욱 크게 감소하였기 때문으로 사료된다. W 과 poly-Si 의 식각 특성을 이해하기 위하여 X -ray photoelectron spectroscopy (XPS)를 사용하였으며, 식각 전후의 etch depth 를 측정하기 위하여 stylus p pmfilometeT 를 이용하였다.