• 제어로봇시스템학회:학술대회논문집
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• 1997.10a
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• pp.520-523
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• 1997

This paper presents FPGA implementation of fuzzy controller using Product-Sum inference method. Product-Sum inference method has much better performance than other inference methods. This fuzzy controller is composed of several digital modules, e.g. fuzzifier, rule base, adder, multiplier, select center and divider, and is operated by error and error variation. We synthesized the fuzzy controller and performed wave simulation using Xilinx VHDL tool(ViewLogic, ViewSim).

• Communications for Statistical Applications and Methods
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• v.6 no.2
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• pp.487-500
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• 1999

We propose a class of hierarchical Bayes estimators of the error variance under the relative squared error loss in balanced fixed-effects two-way analysis of variance models. Also we provide analytic expressions for the risk improvement of the hierarchical Bayes estimators over multiples of the error sum of squares. Using these expressions we identify a subclass of the hierarchical Bayes estimators each member of which dominates the best multiple of the error sum of squares which is known to be minimax. Numerical values of the percentage risk improvement are given in some special cases.

• Korean Journal of Remote Sensing
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• v.33 no.5_1
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• pp.495-506
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• 2017

This study was carried out to effectively perform relative color correction for high-resolution aerial ortho image. For this study, relative geometrical error between adjacent images was analyzed. The block sum method is proposed to reduce the relative geometrical error. We used the regression coefficients determined based on the block sum size to perform the color correction. As a result, it was confirmed that the relative color correction was visually performed well. Quantitative analysis was performed through histogram similarity analysis. It is proved that block sum method is useful for relative color correction. Particularly, the block sum size was very important to correct color based on the amount of relative geometrical error.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.5C
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• pp.423-431
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• 2010

In this paper, a modified sum-product algorithm to correct bit errors captured within the trapping sets, which are produced in decoding of low-density parity-check (LDPC) codes, is proposed. Unlike the original sum-product algorithm, the proposed decoding method consists of two stages. Whether the main cause of decoding failure is the trapping sets or not is determined at the first stage. And the bit errors within the trapping sets are corrected at the second stage. In the modified algorithm, the set of failed check nodes and the transition patterns of hard-decision bits are exploited to search variable nodes in the trapping sets. After inverting information of the variable nodes, the sum-product algorithm is carried out to correct the bit errors. As a result of simulation, the proposed algorithm shows continuously improved error performance with increase in the signal-to-noise ratio. It is, therefore, considered that the modified sum-product algorithm significantly reduces or possibly eliminates the error floor in LDPC codes.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.4C
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• pp.414-423
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• 2009

This paper considers a linear precoding scheme that achieves near optimal sum rate. While the minimum mean square error (MMSE) precoding provides the better MSE performance at all signal-to-noise ratio (SNR) than the zero forcing (ZF) precoding, its sum rate shows superior performance to ZF precoding at low SNR but inferior performance to ZF precoding at high SNR, From this observation, we first propose a near optimal linear precoding scheme in terms of sum rate. The resulting precoding scheme regularizes ZF precoding to maximize the sum rate, resulting in better sum rate performance than both ZF precoding and MMSE precoding at all SNR ranges. To find regularization parameters, we propose a simple algorithm such that locally maximal sum rate is achieved. As a low complexity alternative, we also propose a simple power re-allocation scheme in the conventional regularized channel inversion scheme. Finally, the proposed scheme is tested under the presence of channel estimation error. By simulation, we show that the proposed scheme can maintain the performance gain in the presence of channel estimation error and is robust to the channel estimation error.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.15 no.2
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• pp.485-499
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• 2021

Although non-binary low-density parity-check (NB-LDPC) codes have better error-correction capability than that of binary LDPC codes, their decoding complexity is significantly higher. Therefore, it is crucial to reduce the decoding complexity of NB-LDPC while maintaining their error-correction capability to adopt them for various applications. The extended min-sum (EMS) algorithm is widely used for decoding NB-LDPC codes, and it reduces the complexity of check node (CN) operations via message truncation. Herein, we propose a low-cost CN processing method to reduce the complexity of CN operations, which take most of the decoding time. Unlike existing studies on low complexity CN operations, the proposed method employs quick selection algorithm, thereby reducing the hardware complexity and CN operation time. The experimental results show that the proposed selection-based CN operation is more than three times faster and achieves better error-correction performance than the conventional EMS algorithm.

• Communications of Mathematical Education
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• v.35 no.4
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• pp.425-444
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• 2021

In this study, under the assumption that the goal pursued in measurement area can be reached through the composition of the measurement activity considering the mathematical process, the method of summing the interior angles of a triangle using the measurement error was applied to the 4th grade class of the elementary school. Results of the study, first, students were able to recognize the possibility of measurement error by learning the sum of the interior angles of a triangle using the measurement error. Second, the discussion process based on the measurement error became the basis for students to attempt mathematical justification. Third, the manipulation activity using the semicircle was recognized as a natural and intuitive way of mathematical justification by the students and led to generalization. Fourth, the method of guiding the sum of the interior angles of a triangle using the measurement error contributed to the development of students' mathematical communication skills and positive attitudes toward mathematics.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.1
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• pp.97-105
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• 2015

Multiresponse optimization (MRO) seeks to find the setting of input variables, which optimizes the multiple responses simultaneously. The approach of weighted mean squared error (WMSE) minimization for MRO imposes a different weight on the squared bias and variance, which are the two components of the mean squared error (MSE). To date, a weighted sum-based method has been proposed for WMSE minimization. On the other hand, this method has a limitation in that it cannot find the most preferred solution located in a nonconvex region in objective function space. This paper proposes a Tchebycheff metric-based method to overcome the limitations of the weighted sum-based method.

• ETRI Journal
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• v.37 no.1
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• pp.54-60
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• 2015

The use of serial concatenated codes is an effective technique for alleviating the error floor phenomenon of low-density parity-check (LDPC) codes. An enhanced sum-product algorithm (SPA) for LDPC codes, which is suitable for serial concatenated codes, is proposed in this paper. The proposed algorithm minimizes the number of errors by using the failed check nodes (FCNs) in LDPC decoding. Hence, the error-correcting capability of the serial concatenated code can be improved. The number of FCNs is simply obtained by the syndrome test, which is performed during the SPA. Hence, the decoding procedure of the proposed algorithm is similar to that of the conventional algorithm. The error performance of the proposed algorithm is analyzed and compared with that of the conventional algorithm. As a result, a gain of 1.4 dB can be obtained by the proposed algorithm at a bit error rate of $10^{-8}$. In addition, the error performance of the proposed algorithm with just 30 iterations is shown to be superior to that of the conventional algorithm with 100 iterations.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.4
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• pp.1987-2001
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• 2017

Low-density parity-check (LDPC) codes have attracted a great attention because of their excellent error correction capability with reasonably low decoding complexity. Among decoding algorithms for LDPC codes, the min-sum (MS) algorithm and its modified versions have been widely adopted due to their high efficiency in hardware implementation. In this paper, a self-adaptive MS algorithm using the difference of the first two minima is proposed for faster decoding speed and lower power consumption. Finding the first two minima is an important operation when MS-based LDPC decoders are implemented in hardware, and the found minima are often compressed using the difference of the two values to reduce interconnection complexity and memory usage. It is found that, when these difference values are bounded, decoding is not successfully terminated. Thus, the proposed method dynamically decides whether the termination-checking step will be carried out based on the difference in the two found minima. The simulation results show that the decoding speed is improved by 7%, and the power consumption is reduced by 16.34% by skipping unnecessary steps in the unsuccessful iteration without any loss in error correction performance. In addition, the synthesis results show that the hardware overhead for the proposed method is negligible.