• Journal of Satellite, Information and Communications
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• v.10 no.3
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• pp.73-77
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• 2015

In this paper, we present two simulation methods to investigate the effect of excluding bit errors on generating the extrinsic information transfer (EXIT) chart for low density parity check (LDPC) and turbo codes. We utilized the simulation methods including and excluding bit errors to generate EXIT chart which was originally proposed for turbo codes. The generated EXIT charts for LDPC and turbo codes shows that the presented methods appropriately demonstrates the performance behaviours of iterative decoding for LDPC and turbo codes. Analysis on the simulation results demonstrates that the EXIT chart excluding the bit errors shows only a small part of the curves where the amount of information is too large.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.13 no.6
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• pp.535-544
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• 1988

In this paper, the hybrid ARQ scheme, which is incorporated the selective-repeat ARQ system with the finite receiver buffer and the single-error-correcting and double-error-detecting(63.56) cyclic Hamming code system, has been investigated. As a result of simulation, the proposed hybrid ARQ scheme shows that that throughput efficiencies are improved by one error correction, and that the reversed codewords due to retransmission are delivered to the user in order by means of detecting two errors. The hybrid ARQ scheme significantly outperforms the FEC or the ideal selective-repeat ARQ system in the respect of throughput and reliability, especially when the channel error rate is approximately in the range from $10^{-2}$~$10^{-3}$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.333-340
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• 2017

In this paper, we describe HW/SW co-optimizations for reconfigurable application specific instruction-set processors (ASIPs). Based on our previous very long instruction word (VLIW) ASIP, the proposed framework realizes various forward error-correction (FEC) algorithms for wireless communication systems. In order to enhance the energy efficiency, we newly introduce several design methodologies including high-radix algorithms, task-level out-of-order executions, and intensive resource allocations with loop-level rescheduling. The case study on the radix-4 turbo decoding shows that the proposed techniques improve the energy efficiency by 3.7 times compared to the previous architecture.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.12C
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• pp.1633-1641
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• 2004

In satellite digital broadcasting and satellite internet, severe burst errors occur in the high-speed return channel from the satellite to mobiles. In this paper, we analyze the performance of the forward error correction (FEC) coding method in the Rayleigh fading return channel. We first investigate the channel model of Loo, LutB, Vucetic and Corazza. We then compare the performance of the convolutional, Reed-Solomon (RS), convolution-RS concatenation, and Turbo codes in rayleigh fading channel.

• Journal of Satellite, Information and Communications
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• v.1 no.2
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• pp.51-55
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• 2006

Digital satellite communication systems are usually integrated with terrestrial systems to provide various services. In these cases, they should satisfy the performance objectives defined by the terrestrial systems. Recommendation ITU-R S.1062 specifies the error performance objectives of digital satellite communication systems operating below 15 GHz. The error performance are given in terms of bit error probability divided by the number of the average bit errors in the burst ($\alpha$). This paper presents a theoretical method to estimate $\alpha$ that is a very important parameter in the satellite communication systems to analyze the error performance objectives. We show performance estimation result of DVB-RCS turbo code using the presented method, and verify them by comparing to the simulation results.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.1
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• pp.37-42
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• 2019

In this paper, we propose a syndrome decoding scheme that can correct two errors for single error correcting Hamming codes within a code length. The decoding scheme proposed in this paper has the advantage of significantly improving the error rate performance compared to the decoder complexity by correcting multiple errors without substantially increasing the decoding complexity. It is suitable for applications in which the energy use of encoder/decoder is extremely limited and the low error rate performance is required, such as IoT communications and molecular communications. In order to verify the improvement of the error rate performance of the Hamming code with the proposed decoding scheme, we performed simulation on Hamming codes with short code length in the AWGN and BPSK modulation environments. As a result, compared with the conventional decoding method, the proposed decoding scheme showed performance improvement of about 1.1 ~ 1.2[dB] regardless of the code length of the Hamming code.

• Proceedings of the KIEE Conference
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• 2001.07d
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• pp.2493-2495
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• 2001

Burst Error Channel의 에러 정정 기술로써 Reed-Solomon Product Code(RSPC)가 광범위하게 사용되고 있다. 그러나 Random Error Channel과는 달리 Burst Error Channel 상에서 RSPC의 에러 정정 평가 방법에는 많은 어려움이 있다. 우리는 이번 논문에서 Burst Error Channel 상에서 RSPC의 Error Correction Capability의 확률적인 계산 방법을 기술하려 한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.4C
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• pp.191-199
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• 2005

Space-time turbo codes have been studied extensively as a powerful and bandwidth efficient error correction code over the wireless communication environment. In this paper, the efficient algorithm for decoding space-time turbo codes is proposed. The proposed method reduces the computational complexity by approximating a prior information for a iterative decoder. The performance of space-time turbo codes is also analyzed by using the fixed point implementation and the efficient method for approximating the Log-MAP algorithm is proposed. It is shown that the BER performance of the proposed method is close to that of the Log-MAP algorithm.

• Proceedings of the Korea Society of Information Technology Applications Conference
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• 2005.11a
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• pp.77-80
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• 2005

Wireless sensor networks(WSN) technology has various applications such as surveillance and information gathering in the uncontrollable area of human. One of major issues in WSN is the research for reducing the energy consumption and reliability of data. A system with forward error correction(FEC) can provide an objective reliability while using less transmission power than a system without FEC. In this paper, we propose to use LDPC codes of various code rate(0.53, 0.81, 0.91) for FEC for WSN. Also, we considered node-to-node interference in addition to AWGN channel. The proposed system has not only high reliable data transmission at low SNR, but also reduced transmission power usage.

• Proceedings of the IEEK Conference
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• 2001.06a
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• pp.205-208
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• 2001

According to the IMT-2000 specification of 3GPP(3rd Generation Partnership Project) and 3GPP2, Turbo codes is selected as a FEC(forward error correction) code for even higher reliable data communication. In 3GPP complied IMT-2000 system, channel coding under consideration is the selective use of convolutional coding and Turbo codes of 1/3 code rate with 4 constraint length. Suggesting a new path metric normalization method, we achieved a low complexity and high performance SOVA decoder for Turbo Codes, Further more, we analyze the decoding performance with respect to update depth and find out the optimal value of it by using computer simulation. Based on the simulation result, we designed a SOVA decoder using VHDL and implemented it into the Altera EPF10K100GC503FPGA.