• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2002.05a
• /
• pp.635-637
• /
• 2002

본 논문에서는 차세대이동통신에서 고속·고품질 전송을 실현하기 위해, 전송환경에 맞게 최적의 변조 다치 수를 선택하는 적응변조방식에 에러 정정 부호기법을 제안하였다. 고속ㆍ고품질화의 한 방법으로서, 에러 정정 부호를 적응한 시스템을 생각할 수 있는데, 본 논문에서 방식은 변조 파라미터가 변화하는 것에 의해 적응변조방식에 효과적인 BCH 부호 기법 및 RS 부호 기법을 적용한 경우의 전송 품질을 검토하였다.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.28 no.10A
• /
• pp.788-795
• /
• 2003

We analyze the performance of a truncated power controlled CDMA(code division multiple access) cellular systems with base station antenna arrays. Erlang capacity and the channel capacity which is a maximum date rate to maintain almost error free communication are analytically derived. The numerical results show there can be a substantial increase in Erlang capacity and in channel capacity by antenna arrays incorporating with the truncated power control scheme.

• Journal of the Institute of Convergence Signal Processing
• /
• v.6 no.4
• /
• pp.206-211
• /
• 2005

We describe the design for a correlator and an access code generator in bluetooth system. These are used for a connection setting, a packet decision and a clock synchronization between Bluetooth units. The correlator consists of two blocks; carry save adder based on Wallace tree and threshold-value decision block. It determines on an useful packet and clock-synchronization for input signal of 1.0Mbps through the sliding-window correlating. The access-code generator also consists of two blocks; BCH(Bose-Chadhuri-Hocquenghem) cyclic encoder and control block. It generates the access-codes according to four steps' generation process based on Bluetooth standard. In order to solve synchronization problem, we make use of any memory as a pseudo random sequence. The proposed correlator and access-code generator were coded with VHDL. An FPGA Implementation of these modules and the simulation results are proved by Xilinx chip. The critical delay and correlative margin based on synthesis show the 4.689ns and the allowable correlation-error up to 7-bit.

• 제어로봇시스템학회:학술대회논문집
• /
• 2003.10a
• /
• pp.2632-2635
• /
• 2003

This paper designs a software signal generator for the new GPS L2 civil signal. The CM/CL code and the message structure of L2CS described in GPS ICD PPIRN-200C-007 are used in designing the signal generator. The output of the GPS signal generator is designed as the sampled IF data with the sampling frequency 5.7MHz and stored in the binary data format. By analyzing both the spectrum characteristics of the output signal and the correlation properties of the CM/CL code, the validation of the designed GPS signal generator is shown. It should be mentioned that the modeling of the GPS satellite constellation and the error sources remains for implementing the software space segment of GPS.

• Proceedings of the Korea Multimedia Society Conference
• /
• 2003.11b
• /
• pp.557-560
• /
• 2003

In this paper, we developed an editor and running engine for the SoftPLC. LD is the most popular standard IEC 1131-3 PLC language in Korea and used over 90% among the 5 PLC languages. In this paper, we have developed the ISPLC(Intelligent Agent System based Software Programmable Logic Controller). In ISPLC system, LD programmed by a user is converted to IL, which is one of intermediate codes, and IL is converted to the standard C code which can be used in a commercial editor such as visual C++. In ISPLC, the detection of logical error in high level programming(C) is more efficient than PLC programming itself. ISPLC provide easy programming platform to such beginner as well as professionals. The study of code conversion of LD-> U->C is firstly tried in the world as well as KOREA.

• 제어로봇시스템학회:학술대회논문집
• /
• 2001.10a
• /
• pp.158.1-158
• /
• 2001

An algorithmic gray code analog-to-digital converter (ADC), which is based on gray coding, is proposed in this article. The realization method makes use of a MOS triangular function circuit to provide a high-speed operation and low accumulated error. The proposed ADC is simple, small in size and suitable for fabrication using a standard CMOS process. Simulation results showing the performances of the proposed circuit are also included.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.21 no.7
• /
• pp.1814-1819
• /
• 1996

This paper describes a dnw serial interface system which uses comma free code. Typically parallel 25 pin cable and connectors are used to transfer and receive the data between digital systems such as HDVCR, D3VTR and HDTV Receiver.The coaxial cable is more desirable for consumer product applications and also for studio applications where long signal paths and switching are requeired. This serial data trasfer technique is possible the error detection and the self synchronization, also easy edge insertion for PLL control. It is also cost effective because is does not requeire RF PLL, scrambling, and NRZI hardware.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.36 no.4C
• /
• pp.191-196
• /
• 2011

In this paper, we propose a design method of Reed-Solomon (23, 17) decoder for UWB using direct decoding method. The direct decoding algorithm is more efficient for the case of relatively small error correction capability. The proposed decoder requires only 9 $GF(2^m)$ multipliers in obtaining the error-locator polynomial and the error-evaluator polynomial, whereas other decoders need about 20 multipliers. Thus, the attractive feature of this decoder is its remarkable simplicity from the point of view of hardware implementation. Futhermore, the proposed decoder has very simple control circuit and short decoding delay. Therefore this decoder can be implemented by simple hardware and also save buffer memory which stores received sequence.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.40 no.9
• /
• pp.1846-1855
• /
• 2015

In this paper, a precise relative positioning with TD(time differenced) carrier phase measurements from a low-cost GNSS(Global Navigation Satellite System) receiver is proposed and analysed. The proposed method is using carrier phase measurement from a single GNSS receiver that reference receiver is not required and stand alone positioning is possible. TD operation removes the troublesome integer ambiguity resolution problem, and if the time interval is short, other error, such as, ionospheric, tropospheric delay and ephemeris error are effectively eliminated. The error analysis of the proposed method shows that a precise and positioning with carrier phase is possible. The implemented system is evaluated using a real car experiments. The results show that the horizontal positioning error was less than 3m during 10 minutes experiments, which is 4 times more precise than the results of normal code based absolute positioning.

• Journal of the Korean Society for Aeronautical & Space Sciences
• /
• v.42 no.5
• /
• pp.398-405
• /
• 2014

Recently the embedded software has been widely applied to the safety-critical systems in aviation and defense industries, therefore, the higher level of reliability, availability and fault tolerance has become a key factor for its implementation into the systems. The integrity of the software can be verified using the static analysis tools. And recent developed static analysis tool can evaluate code integrity through the mathematical analysis method. In this paper we detect the autocode error and violation of coding rules using the formal verification tool, Polyspace(R). And the fundamental errors on the flight control law model have been detected and corrected using the formal verification results. As a result of verification process, FBW helicopter control law autocode can ensure code integrity.