• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.7A
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• pp.568-573
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• 2009

This paper presents a step-down DC-DC converter with On-chip Compensation for battery-operated portable electronic devices which are designed in O.13um CMOS standard process. In an effort to decrease system volume, this paper proposes the on chip compensation circuit using capacitor multiplier method. Capacitor multiplier method can minimize error amplifier's compensation capacitor size by 10%. It allows the compensation block of DC-DC converter be easily integrated on a chip and occupy less layout area. But capacitor multiplier operation reduces DC-DC converter efficiency. As a result, this converter shows maximum efficiency over 87.2% for the output voltage of 1.2V (input voltage : 3.3V), maximum load current 500mA, and 25mA output ripple current. This voltage mode controled buck converter has 1MHz switching frequency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.4C
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• pp.401-407
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• 2010

In this paper, we consider a low-complex companding technique for peak-to-average power ratio (PAPR) reduction in orthogonal frequency division multiplexing (OFDM) systems. For the technique, we propose a novel companding function to compensate the problem of the conventional companding functions which are difficult to design complying with system requirements and deteriorate the bit error rate (BER) performance significantly. The proposed scalable companding function can provide an arbitrary value of the maximum PAPR with which the BER performance changes gracefully. In addition, the proposed companding function can be designed readily according to the PAPR and BER performance required by the system and is observed to provide better BER performance than the conventional clipping and $\mu$-low companding schemes under the similar PAPR condition.

• ETRI Journal
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• v.29 no.5
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• pp.633-640
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• 2007

We report an experimental demonstration of 40 Gbps all-optical 3R regeneration with all-optical clock recovery based on InP semiconductor devices. We also obtain alloptical non-return-to-zero to return-to-zero (NRZ-to-RZ) format conversion using the recovered clock signal at 10 Gbps and 40 Gbps. It leads to a good performance using a Mach-Zehnder interferometric wavelength converter and a self-pulsating laser diode (LD). The self-pulsating LD serves a recovered clock, which has an rms timing jitter as low as sub-picosecond. In the case of 3R regeneration of RZ data, we achieve a 1.0 dB power penalty at $10^{-9}$ BER after demultiplexing 40 Gbps to 10 Gbps with an eletroabsorption modulator. The regenerated 3R data shows stable error-free operation with no BER floor for all channels. The combination of these functional devices provides all-optical 3R regeneration with NRZ-to-RZ conversion.

• Journal of the Optical Society of Korea
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• v.14 no.3
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• pp.240-244
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• 2010

In this work, we used PWM sampling for demodulation of a fiber-optic interferometric current transformer. The interference signal from a fiber-optic CT is sampled with PWM triggers that produce a 90-degree phase difference between two consecutively sampled signals. The current-induced phase is extracted by applying an arctangent demodulation and a phase unwrapping algorithm to the sampled signals. From experiments using the proposed demodulation, we obtained phase measurement accuracy and a linearity error, in AC current measurements, of ~2.35 mrad and 0.18%, respectively. The accuracy of the proposed method was compared with that of a lock-in amplifier demodulation, which showed only 0.36% difference. To compare the birefringence effects of different fiber-optic sensor coils, a flint glass fiber and a standard single-mode fiber were used under the same conditions. The flint glass fiber coil with a Faraday rotator mirror showed the best performance. Because of the simple hardware structure and signal processing, the proposed demodulation would be suitable for low-cost over-current monitoring in high voltage power systems.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.49 no.1
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• pp.54-61
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• 2000

Conventionally, ZVS FB DC/DC converter was controlled by monolithic IC UC3879, which includes the functions of oscillator, error amplifier and phase-shift circuit. Also, microprocessor and DSP have been widely used for the remote control and for the immediate waveform control in ZVS FB DC/DC converter. However the conventional microprocessor controller is complex and difficult to control because the controller consists of analog and digital parts. In the case of the control of FB DC/DC converter, the output is required of driving a direct signal to the switch drive circuits by the digital controller. So, this paper presents the method and realization of designing the digital-to-phase shift PWM circuit controlled by DSP (TMX320C32) in a 2,500A, 40㎾ ZVS FB DC/DC converter.

• Journal of the Korean Society of Industry Convergence
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• v.24 no.5
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• pp.641-644
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• 2021

Wearable devices and IoT are being utilized in various fields, where all systems are developing in the direction of multi-functionality, low power consumption, and high speed. In this paper, we propose a DC -DC Step-down C onverter for IoT smart devices. The proposed DC -DC Step-down converter is composed of a control block of the power supply stage. It also consists of an overheat protection circuit, under-voltage protection circuit, an overvoltage protection circuit, a soft start circuit, a reference voltage circuit, a lamp generator, an error amplifier, and a hysteresis comparator. The proposed DC-DC converter was designed and fabricated using a Magnachip / Hynix 180nm CMOS process, 1-poly 6-metal, the measured results showed a good match with the simulation results.

• Journal of IKEEE
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• v.23 no.2
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• pp.552-556
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• 2019

This paper present a capless low drop out regulator (LDO) that improves the load transient response characteristics by using a current regulator. A voltage regulator circuit is placed between the error amplifier and the pass transistor inside the LDO regulator to improve the current characteristics of the voltage line, The proposed fast transient LDO structure was designed by a 0.18 um process with cadence's virtuoso simulation. according to test results, the proposed circuit has a improved transient characteristics compare with conventional LDO. the simulation results show that the transient of rising increases from 1.954 us to 1.378 us and the transient of falling decreases from 19.48 us to 13.33 us compared with conventional capless LDO. this Result has improved response rate of about 29%, 28%.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.13 no.6
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• pp.2908-2924
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• 2019

Multiple input multiple output orthogonal frequency division multiplexing (MIMO-OFDM) is widely applied in wireless communication by virtue of its excellent properties in data transmission rate and transmission accuracy. However, as a major drawback of MIMO-OFDM systems, the high peak-to-average power ratio (PAPR) complicates the design of the power amplifier at the receiver end. Some available PAPR reduction methods such as selective mapping (SLM) suffer from high computational complexity. In this paper, a low-complexity SLM method based on active constellation extension (ACE) and joint space-time selective mapping (AST-SLM) for reducing PAPR in Alamouti STBC MIMO-OFDM systems is proposed. In SLM scheme, two IFFT operations are required for obtaining each transmission sequence pair, and the selected phase vector is transmitted as side information(SI). However, in the proposed AST-SLM method, only a few IFFT operations are required for generating all the transmission sequence pairs. The complexity of AST-SLM is at least 86% less than SLM. In addition, the SI needed in AST-SLM is at least 92.1% less than SLM by using the presented blind detection scheme to estimate SI. We show, analytically and with simulations, that AST-SLM can achieve significant performance of PAPR reduction and close performance of bit error rate (BER) compared to SLM scheme.

• ETRI Journal
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• v.42 no.6
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• pp.943-950
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• 2020

We propose 8.2-GHz band radar RFICs for an 8 × 8 phased-array frequency-modulated continuous-wave receiver developed using 65-nm CMOS technology. This receiver panel is constructed using a multichip solution comprising fabricated 2 × 2 low-noise amplifier phase-shifter (LNA-PS) chips and a 4ch RX front-end chip. The LNA-PS chip has a novel phase-shifter circuit for low-voltage operation, novel active single-to-differential/differential-to-single circuits, and a current-mode combiner to utilize a small area. The LNA-PS chip shows a power gain range of 5 dB to 20 dB per channel with gain control and a single-channel NF of 6.4 dB at maximum gain. The measured result of the chip shows 6-bit phase states with a 0.35° RMS phase error. The input P1 dB of the chip is approximately -27.5 dBm at high gain and is enough to cover the highest input power from the TX-to-RX leakage in the radar system. The gain range of the 4ch RX front-end chip is 9 dB to 30 dB per channel. The LNA-PS chip consumes 82 mA, and the 4ch RX front-end chip consumes 97 mA from a 1.2 V supply voltage. The chip sizes of the 2 × 2 LNA-PS and the 4ch RX front end are 2.39 mm × 1.3 mm and 2.42 mm × 1.62 mm, respectively.

• Journal of IKEEE
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• v.25 no.1
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• pp.201-205
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• 2021

In this paper present Low Drop-Out (LDO) regulator that improved load transient characteristics due to the push-pull detection structure. The response characteristic of the voltage delta value is improved due to the proposed push-pull sensing circuit structure between the input terminal of the LDO regulator pass transistor and the output terminal of the internal error amplifier. Voltage value has improved load transient characteristics than conventional LDO regulator. Compared to the conventional LDO regulator, it has an improved response speed of approximately 244 ns at rising time and approximately 90 ns at falling time. The proposed circuit was simulated by the samsung 0.13um process using Cadence's Specter and Virtuoso simulator.