• Title/Summary/Keyword: Error Counter

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Design of Temperature System Using BiCMOS (BiCMOS를 이용한 온도 센서 시스템의 설계)

  • 최진호
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.52 no.8
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    • pp.330-334
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    • 2003
  • A Temperature sensor system in which the digital output signal is proportional to the operating temperature is designed. The temperature sensor system is designed by using BiCMOS technology and consists of temperature sensor, voltage-to-frequency converter and counter. The proposed temperature sensor system has error less than $1^{\circ}C$ in the temperature range $-25^{\circ}C$ to $55^{\circ}C$.

Developement of Soil Moisture Meter using Capacitance Probe (정전용량 탐침을 이용한 토양수분 측정장치 개발)

  • Kim, Ki-Bok;Lee, Nam-Ho;Lee, Jong-Whan;Lee, Seung-Seok
    • Proceedings of the Korean Society of Agricultural Engineers Conference
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    • 2001.10a
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    • pp.65-68
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    • 2001
  • This study was conducted to develop a soil moisture meter using capacitance probe. A parallel cylinder type capacitance probe (C-probe) was fabricated The 5 MHz of crystal oscillator was constructed to detect the capacitance change of the C-probe with moist soil. A third order polynomial regression model for volumetric water content having oscillation frequency changes at 5 MHz as independent variables presented the determination coefficient of 0.979 and root mean square error of $0.031\;cm^{3}cm^{3}$ for all soil samples. A prototype soil moisture meter consisting of the sample container, C-probe, oscillator, frequency counter and related signal procession units presented the correlation coefficient of 0.987 and the root mean square error of $0.032\;cm^{3}cm^{3}$ as compared with the oven drying method for unknown soil samples.

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Design of Timing Register Structure for Area Optimization of High Resolution and Low Power SAR ADC (고해상도 저전력 SAR ADC의 면적 최적화를 위한 타이밍 레지스터 구조 설계)

  • Min, Kyung-Jik;Kim, Ju-Sung;Cho, Hoo-Hyun;Pu, Young-Gun;Hur, Jung;Lee, Kang-Yoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.8
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    • pp.47-55
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    • 2010
  • In this paper, a timing register architecture using demultiplexer and counter is proposed to reduce the area of the high resolution SAR type analog to digital converter. The area and digital power consumption of the conventional timing register based on the shift register is drastically increased, as the resolution is increased. On the other hand, the proposed architecture results in reduction of the area and the power consumption of the error correction logic of the SAR ADC. This chip is implemented with 0.18 um CMOS process. The area is reduced by 5.4 times and the digital power consumption is minimized compared with the conventional one. The 12 bits SAR ADC shows ENOB of 11 bits, power consumption of 2 mW, and conversion speed of 1 MSPS. The die area is $1 mm{\times}1mm$.

A CMOS Duty Cycle Corrector Using Dynamic Frequency Scaling for Coarse and Fine Tuning Adjustment (코오스와 파인 조정을 위한 다이나믹 주파수 스케일링 기법을 사용하는 CMOS 듀티 사이클 보정 회로)

  • Han, Sangwoo;Kim, Jongsun
    • Journal of the Institute of Electronics and Information Engineers
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    • v.49 no.10
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    • pp.142-147
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    • 2012
  • This paper presents a mixed-mode CMOS duty-cycle corrector (DCC) circuit that has a dynamic frequency scaling (DFS) counter and coarse and fine tuning adjustments. A higher duty-cycle correction accuracy and smaller jitter have been achieved by utilizing the DFS counter that reduces the bit-switching glitch effect of a digital to analog converter (DAC). The proposed circuit has been designed using a 0.18-${\mu}m$ CMOS process. The measured duty cycle error is less than ${\pm}1.1%$ for a wide input duty-cycle range of 25-75% over a wide freqeuncy range of 0.5-1.5 GHz.

Performance testing of a FastScan whole body counter using an artificial neural network

  • Cho, Moonhyung;Weon, Yuho;Jung, Taekmin
    • Nuclear Engineering and Technology
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    • v.54 no.8
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    • pp.3043-3050
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    • 2022
  • In Korea, all nuclear power plants (NPPs) participate in annual performance tests including in vivo measurements using the FastScan, a stand type whole body counter (WBC), manufactured by Canberra. In 2018, all Korean NPPs satisfied the testing criterion, the root mean square error (RMSE) ≤ 0.25, for the whole body configuration, but three NPPs which participated in an additional lung configuration test in the fission and activation product category did not meet the criterion. Due to the low resolution of the FastScan NaI(Tl) detectors, the conventional peak analysis (PA) method of the FastScan did not show sufficient performance to meet the criterion in the presence of interfering radioisotopes (RIs), 134Cs and 137Cs. In this study, we developed an artificial neural network (ANN) to improve the performance of the FastScan in the lung configuration. All of the RMSE values derived by the ANN satisfied the criterion, even though the photopeaks of 134Cs and 137Cs interfered with those of the analytes or the analyte photopeaks were located in a low-energy region below 300 keV. Since the ANN performed better than the PA method, it would be expected to be a promising approach to improve the accuracy and precision of in vivo FastScan measurement for the lung configuration.

A Design of Lightweight RFID Authentication Protocol Errors Correction Using Re-Counter (재카운터를 이용해 오류를 수정하는 경량화 RFID 인증 프로토콜 설계)

  • OH, Gi-Oug
    • Journal of the Korea Society of Computer and Information
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    • v.16 no.4
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    • pp.149-157
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    • 2011
  • Passive tags are inferior to active tags in processing efficiency, so they have difficulty in largevolume processing. The proposed protocol reduces the volume of computation in passive tags and, at the same time, improves authentication for enhanced safety and security. That is, different from existing RFID protocols that return the same value even if an error happens when the reader reads a tag, the improved RFID security protocol returns a new value using a re-counter and processes the computation part of a tag in the reader or in a back.end system. Even if the information of a tag is acquired by an malicious way, it is not actual information but encrypted information that is not usable. In addition, even if tag information is read in sequence, it is changed in each read, so the protocol is safe from Location Tracking.

Design of Digital PLL using Binary Phase-Frequency Detector and Counter for Digital Phase Detection (이진 위상-주파수 검출기와 카운터를 이용한 디지털 위상 고정 루프 회로 설계)

  • Han, Jong-Seok;Yoon, Kwan;Kang, Jin-Ku
    • Journal of IKEEE
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    • v.16 no.4
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    • pp.322-327
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    • 2012
  • In this paper, a digital phase-locked loop(Digital-PLL) circuit with a new phase-to-digital converter(P2D) is described. The proposed digital PLL is composed a P2D, a digital loop filter(DLF), and a digitally controlled oscillator(DCO). The P2D generates a digital code for a phase error. The proposed P2D used a binary phase frequency detector(BPFD) and a counter in place of a time-to-digital converter(TDC) for simple structure, compact area and low power consumption. The proposed circuit was designed with CMOS 0.18um process. The simulation shows the circuit operates with the 1.0 to 2.2GHz with the power consumption of 16.2mW at 1.65GHz and the circuit occupies the chip area of $0.096mm^2$.

Implementation of Digital Signal Processing Board Suitable for a Semi-active Laser Tracking to Detect a Laser Pulse Repetition Frequency and Optimization of a Target Coordinates (반능동형 레이저 유도 추적에 적합한 레이저 펄스 반복 주파수 검출을 위한 디지털 신호처리 보드 구현 및 표적 좌표 최적화)

  • Lee, Young-Ju;Kim, Yong-Pyung
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.64 no.4
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    • pp.573-577
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    • 2015
  • In this paper, we propose a signal processing board suitable for a semi-active laser tracking to detect an optical signal generated from the laser target designator by applying an analog trigger signal, the quadrant photodetector and a high speed ADC(analog-digital converter) sampling technique. We improved the stability by applying the averaging method to minimize the measurement error of a gaussian pulse. To evaluate the performances of the proposed methods, we implemented a prototype board and performed experiments. As a result, we implemented a frequency counter with an error 14.9ns in 50ms. PRF error code has a stability of less than 1.5% compared to the NATO standard. Applying the three point averaging method to ADC sampling, the stability of 28% in X-axis and 22% in Y-axis than one point sampling was improved.

An Analysis of Error Factors for Software Based Pseudolite Time Synchronization Performance Evaluation (소프트웨어 기반 의사위성 시각동기 기법 성능평가를 위한 오차 요소 분석)

  • Lee, Ju Hyun;Lee, Sun Yong;Hwang, Soyoung;Yu, Dong-Hui;Park, Chansik;Lee, Sang Jeong
    • Journal of Advanced Navigation Technology
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    • v.18 no.5
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    • pp.429-436
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    • 2014
  • This paper proposes three methods of the time synchronization for Pseudolite and GPS and analyzes pseudolite time synchronization error factors for software based performance evaluation on proposed time synchronization methods. Proposed three time synchronization methods are pseudolite time synchronization station construction method, method by using UTC(KRIS) clock source and GPS timing receiver based time synchronization method. Also, we analyze pseudolite time synchronization error factors such as errors of pseudolite clock and reference clock, time delay as clock transmission line, measurement error of time interval counter and error as clock synchronization algorithm to design simulation platform for performance evaluation of pseudolite time synchronization.

Measurement of Inertia of Turbocharger Rotor in a Passenger Vehicle (승용차용 터보과급기 로터의 관성모멘트 측정)

  • Chung, Jin Eun;Lee, Sangwoon
    • Transactions of the Korean Society of Automotive Engineers
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    • v.24 no.1
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    • pp.33-38
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    • 2016
  • The turbocharger is an essential component to realize the engine down-sizing. The moment of inertia of turbocharger rotor is an important parameter with respect to acceleration performance of the vehicle. It can be calculated from the CAD software based the geometry data and the material properties. But the accurate value of the inertia of turbocharger rotor must be measured through the experimental method. In this study, the measurement of moment of inertia of turbocharger rotor for 2.0 L spark-ignition engine was carried out. First, an experimental equipment using a trifilar method was designed and fabricated. Some optical devices, that is, photo sensor, counter, convex lens, etc, were used to increase the accuracy of the measurement. Second, error sensitivity for the equipment was analyzed. The error of period time and the radius can give big affects to the accuracy of the moment of inertia. When the amount of error of these two were each 1.0 %, maximum error of the moment of inertia was under 3.0 %. Third, the calibration for the equipment was performed using a calibration rotor which has similar shape to turbine rotor but simple. Calculated value from CAD software and measured one for the calibration rotor were compared. The total error of the equipment and the measurement is about 1.3 %. This result shows that the equipment can give the good result with resonable accuracy. Finally the moment of inertia of the turbine rotor and compressor wheel were measured. The coefficient of variations, the ratio of standard deviation to mean value, were reasonably small at 0.57 % and 0.73 % respectively. Therefore this equipment is suitable for the measurement of the moment of inertia of the turbine rotor and compressor wheel.