• 제목/요약/키워드: Epitaxial layer

검색결과 335건 처리시간 0.022초

원통형 접합경계를 갖는 punchthrough 다이오드의 항복전압에 대한 해석적 계산 (Analytical Calculation for the Breakdown Voltage of the Punchthrough Diode with Cylindrical Junction Edge)

  • 김두영;김한수;최연익;한민구
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1994년도 하계학술대회 논문집 C
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    • pp.1448-1450
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    • 1994
  • The breakdown voltages of punchthrough-mode diodes with cylindrical junction are analytically calculated, The proposed method, which is based on th Gauss's law, estimates the lateral expansion of the depletion region as well as the electric field and the charge distribution. The proposed method is given in terms of epitaxial layer width, the epitaxial layer doping concentration, and curvature radius of the junction edge. The calculation results agree well with the MEDICI simulation results for various device parameters.

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에피박막 결함이 탄화규소 쇼트키 다이오드소자의 항복전압 특성에 미치는 영향 (Influence of the epitaxial-layer defects on the breakdown characteristics of the SiC schottky diode)

  • 정희종;방욱;김남균;김상철;서길수;김형우;김은동;이용재
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2004년도 추계학술대회 논문집 Vol.17
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    • pp.285-288
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    • 2004
  • 탄화규소 기판의 에피 박막결함으로는 dislocation, micropipe, pin-hole 및 에피층 표면의 여러 가지 결함들이 있다. 이러한 결함들이 탄화규소 쇼트키 다이오드의 항복전압과 어떠한 상관관계가 존재하는지 알아 보기 위해 탄화규소 쇼트키 다이오드를 제작하고, 제작된 소자의 항복전압을 측정하였다. 에피 박막내의 결함 분포를 알아보기 위해 항복전압 측정후 KOH 용액을 이용한 SiC의 에칭을 수행하였으며, 제작된 여러소자들에 대해 항복전압의 분포도와 결함 분포도를 작성, 비교 관찰하였다.

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Chemical Doping of Graphene by Altretamine(2,4,6-Tris [dimethylamino]-1,3,5-Triazine)

  • Park, Sun-Min;Yang, Se-Na;Lim, Hee-Seon;Lee, Han-Gil
    • Bulletin of the Korean Chemical Society
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    • 제32권7호
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    • pp.2199-2202
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    • 2011
  • The electronic properties of altretamine(2,4,6-tris [dimethylamino]-1,3,5-triazine) adsorbed on epitaxial graphene (EG) were investigated by core-level photoemission spectroscopy (CLPES) in conjunction with low energy electron diffraction (LEED). We found that altretamine molecule adsorbed onto interface layer (S1) of graphene as we confirm decrement of S1 peak using CLPES and haziness of LEED pattern. Moreover, the measured work function changes verified that increased adsorption of the altretamine on graphene layer showed n-type doping characteristics due to charge transfer from altretamine to graphene through the nitrogens. Two distinct nitrogen bonding feature associated with the N 1s peak was clearly observed in the core-level spectra indicating two different chemical environments.

Silicon Carbide 쇼트기 정류기의 모델링 (Modeling the Silicon Carbide Schottky Rectifiers)

  • 이유상;최연익;한민구
    • 대한전기학회논문지:전기물성ㆍ응용부문C
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    • 제49권2호
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    • pp.78-81
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    • 2000
  • The closed-form analytic solutions for the breakdown voltage of 6H-SiC RTD(silicon carbide reachthrough diode) having metal$-n^--n^+$ Schottky structure or $p^+-n^--n^+$, are successfully derived by solving impact ionization integral using an effective ionization coefficient. For the lightly doped n- epitaxial layer, the breakdown voltage of SiC RTD are nearly constant with the increased doping concentration while the breakdown voltages decrease for the heavily doped epitaxial layer.

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실리콘 에피층 성장과 실리콘 에칭기술을 이용한 Bare Chip Burn-In 테스트용 인터컨넥션 시스템의 제조공정 (Fabrication Processes of Interconnection Systems for Bare Chip Burn-In Tests Using Epitaxial Layer Growth and Etching Techniques of Silicon)

  • 권오경;김준배
    • 한국표면공학회지
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    • 제28권3호
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    • pp.174-181
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    • 1995
  • Multilayered silicon cantilever beams as interconnection systems for bare chip burn-in socket applications have been designed, fabricated and characterized. Fabrication processes of the beam are employing standard semiconductor processes such as thin film processes and epitaxial layer growth and silicon wet etching techniques. We investigated silicon etch rate in 1-3-10 etchant as functions of doping concentration, surface mechanical stress and crystal defects. The experimental results indicate that silicon etch rate in 1-3-10 etchant is strong functions of doping concentration and crystal defect density rather than surface mechanical stress. We suggested the new fabrication processes of multilayered silicon cantilever beams.

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소자분리를 위한 선택적 실리콘 에피택시 (Selective Si Epitaxy for Device Isolation)

  • 양전욱;조경익;박신종
    • 대한전자공학회논문지
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    • 제23권6호
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    • pp.801-806
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    • 1986
  • The effect of SiH2Cl2 -HCl gas on the growth rate of epitaxial layer is studied. The temperature, pressure and gas mixing ratio of SiH2Cl2 and HCl are varied to study the growth rate dependence and selective Si epitaxy. The P-n junction diode is fabricated on the epitaxial layer and electrical characteristics are examined. Also, using selective Si epitaxy, a possibility of thin dielectric isolation process, that gives an independent isolation width on the mask dimension, is examined.

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전자빔 증착법으로 이축배향된 Ni-3%W 기판 위에 높은 증착률로 제조된 $CeO_2$ 완충층에 대한 연구 (A study on $CeO_2$ buffer layer on biaxially textured Ni-3%W substrate deposited by electron beam evaporation with high deposition rate)

  • 김혜진;이종범;김병주;홍석관;이현준;권병국;이희균;홍계원
    • 한국초전도ㆍ저온공학회논문지
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    • 제13권1호
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    • pp.1-5
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    • 2011
  • [ $CeO_2$ ]has been widely used for single buffer layer of coated conductor because of superior chemical and structural compatibility with $ReBa_2Cu_3O_{7-{\delta}}$(Re=Y, Nd, Sm, Gd, Dy, Ho, etc.). But, the surface of $CeO_2$ layer showed cracks because of the large difference in thermal expansion coefficient between metal substrate and deposited $CeO_2$ layer, when thickness of $CeO_2$ layer exceeds 100 nm on the biaxially textured Ni-3%W substrate. The deposition rate has been limited to be less than 6 $\AA$/sec in order to get a good epitaxy. In this research, we deposited $CeO_2$ single buffer layers on biaxially textured Ni-3%W substrate with 2-step process such as thin nucleation layer(>10 nm) with low deposition rate(3 $\AA$/sec) and thick homo epitaxial layer(>240 nm) with high deposition rate(30 $\AA$/sec). Effect of deposition temperature on degree of texture development was tested. Thick homo epitaxial $CeO_2$ layer with good texture without crack was obtained at $600^{\circ}C$, which has ${\Delta}{\phi}$ value of $6.2^{\circ}$, ${\Delta}{\omega}$ value of $4.3^{\circ}$ and average surface roughness(Ra) of 7.2 nm within $10{\mu}m{\times}10{\mu}m$ area. This result shows the possibility of preparing advanced Ni substrate with simplified architecture of single $CeO_2$ layer for low cost coated conductor.