• Journal of information and communication convergence engineering
• /
• 제8권1호
• /
• pp.116-121
• /
• 2010

New teaching and studying methods using educational contents are gradually widespread with the advancement of information and communication technology. As educational contents, in this paper, we design and implement linguistic contents for studying essential expressions applied to various situations of real life. In detail, the linguistic contents are run on web environments, and have suitable animations for learning essential expressions based on several foreign languages in contextual dialogues. Also, useful functions are included in contents to reinforce what users have learned.

• International Journal of Control, Automation, and Systems
• /
• 제1권3호
• /
• pp.339-350
• /
• 2003

In this paper, we propose a simultaneous multithreading (SMT) architecture that improves instruction throughput by exploiting instruction level parallelism (ILP) and thread level parallelism (TLP). The proposed architecture issues and completes instructions belonging to the same thread in exact program order. The issue and completion policy greatly reduces the design complexity and hardware cost of our architecture, compared with others that employ out-of-order issue and completion. On the other hand, when the instructions belong to different threads, the issue and completion orders for those instructions may not necessarily be identical to the fetch order. The processor issues instructions simultaneously from multiple threads to functional units by exploiting ILP and TLP, and by dynamic resource sharing. That parallel execution notably improves performance and resource utilization with minimal additional hardware cost over the conventional superscalar processors. This paper proposes an SMT architecture with grouping as well as one without grouping. Without grouping, all threads dynamically and flexibly share most resources. On the other hand, in the SMT architecture with grouping, in which resources and threads are divided into several groups for design simplification, resources are shared only among threads belonging to the same group as those resources. Simulation results show that our processors with four and eight threads improve performance by three or more times over the conventional superscalar processor with comparable execution resources and policies, and that reasonable grouping reduces the design complexity of SMT processors with little negative effect on performance.

• 한국산학기술학회논문지
• /
• 제15권7호
• /
• pp.4573-4579
• /
• 2014

21세기 교육은 객관적 지식이나 정보를 전달하는 것에서 학습자들의 비판적사고력과 문제해결 능력을 배양하는 것으로 바뀌고 있다. 더욱이 대학교육에서는 학습자들이 졸업 후 진출하게 될 분야에서 담당하게 될 실제적인 업무를 미리 경험하게하고 자기주도적 학습과 협동학습 능력을 배양할 수 있는 학습자 중심 교육환경의 필요성이 대두되고 있다. PBL은 현재 학습자가 처한 상황을 고려하여 학습자의 흥미를 이끌어 낼 수 있는 현실적이고 실제적인 문제에 관심을 가진다. PBL에서 학습자는 일방적인 지식을 습득하기보다는 다양한 생각과 배경지식을 가진 동료 학습자들과 시식을 공유하고 의미를 협상해 나가는 과정을 통해 협력적 지식을 구축하는 사회적 학습을 경험한다. 이러한 PBL의 장점으로 인해 학교 현장에서 PBL방법의 활용도가 점차 확대되고 있다. 그러나 공학교육에서는 PBL방법이 활동되지 못하고 있다. 따라서 이러한 현 상황을 개선하기 위한 새로운 방법이나 방안들을 개발하거나 도입하여 이를 활용할 필요가 있다. 본 연구는 현대산업 사회에서 요구하는 창의적 문제 해결 능력을 갖춘 인재를 양성하기 위하여 효율적으로 학습할 수 있도록 하기 위한 방안으로 창의공학설계 교과목에 대한 PBL 교수설계 모형을 개발하였다. 이 모형은 크게 5가지 절차로 구성되어 있는데 즉, 분석, 설계, 개발, 실행, 평가로 구성된다. 개발한 PBL 교수설계 모형에 기반하여 창의 공학 설계 교과목을 설계하였다. 본 연구는 창의공학 설계 수업을 위한 PBL 교수 설계 과정에 초점을 두었다. 이러한 교수 설계가 실효성을 거두기 위해서는 실제 많은 강의 현장에 적용해 보는 연구가 뒷받침되어야 할 것이다.

• 한국콘텐츠학회:학술대회논문집
• /
• 한국콘텐츠학회 2014년도 추계 종합학술대회 논문집
• /
• pp.443-444
• /
• 2014

본 연구는 게임프로그래밍 기본 기술 습득을 위하여 교실 수업에서 학생들이 능동적인 실습으로 진행하는 사례를 교수환경(플립티드러닝), 교과내용(프레임워크기반 게임프로그래밍), 상호작용성, 평가방법 중심으로 기술하고, 성공적인 수업을 위한 관리지침과 기대효과를 제시한다.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2002년도 합동 추계학술대회 논문집 정보 및 제어부문
• /
• pp.365-369
• /
• 2002

In this paper, DC motor controller has been designed by using SoC. SoC is short for System on a chip. This is a methodology that both a processor and some applications are integrated in a chip. In order to design this system based on SoC, PIC 16C57 has been selected as a processor because it has not too many instruction sets and simple data path named a harvard structure. And motor control module has been programmed by using VHDL. The advantages of the design based on SoC are as follows: simple structure, high speed working, easily verifying and simulating the system.

• International Journal of Naval Architecture and Ocean Engineering
• /
• 제5권3호
• /
• pp.364-375
• /
• 2013

Contemporary lectures in undergraduate engineering courses typically focus on teaching major technical knowledge-based theories in a limited time. Therefore, most lectures do not allow the students to gain understanding of how the theories are applied, especially in Naval Architecture and Ocean Engineering departments. Shipyards require students to acquire practical ship design skills in undergraduate courses. To meet this requirement, two lectures are organized by the authors; namely, "Planning Procedure of Naval Architecture & Ocean Engineering" (PNAOE) and "Innovative Ship Design" (ISD). The concept of project-based and collaborative learning is applied in these two lectures. In the PNAOE lecture, sophomores receive instruction in the designing and building of model ships, and the students' work is evaluated in a model ship contest. This curriculum enables students to understand the concepts of ship design and production. In the ISD lecture, seniors learn how to develop their creative ideas about ship design and communicate with members of group. They are encouraged to cooperate with others and understand the ship design process. In the capstone design course, students receive guidance to facilitate understanding of how the knowledge from their sophomore or junior classes, such as fluid mechanics, statics, and dynamics, can be applied to practical ship design. Students are also encouraged to compete in the ship design contest organized by the Society of Naval Architects of Korea. Moreover, the effectiveness of project-based and collaborative learning for enhancing interest in the shipbuilding Industry and understanding the ship design process is demonstrated by citing the PNAOE and ISD lectures as examples.

• Journal of Computing Science and Engineering
• /
• 제8권1호
• /
• pp.34-42
• /
• 2014

Time-predictability of computing is critical for hard real-time and safety-critical systems. However, currently there is no metric available to quantitatively evaluate time-predictability, a feature crucial to the design of time-predictable processors. This paper first proposes the concept of architectural time-predictability, which separates the time variation due to hardware architectural/microarchitectural design from that due to software. We then propose the standard deviation of clock cycles per instruction (CPI), a new metric, to measure architectural time-predictability. Our experiments confirm that the standard deviation of CPI is an effective metric to evaluate and compare architectural time-predictability for different processors.

• Structural Engineering and Mechanics
• /
• 제5권5호
• /
• pp.635-644
• /
• 1997

The paper reviews the implementation and evaluation of exact methods for the computation of transcendental structural eigenvalues, i.e., critical buckling loads and natural frequencies of undamped vibration, on multiple instruction, multiple data parallel computers with distributed memory. Coarse, medium and fine grain parallel methods are described with illustrative examples. The methods are compared and combined into hybrid methods whose performance can be predicted from that of the component methods individually. An indication is given of how performance indicators can be presented in a generic form rather than being specific to one particular parallel computer. Current extensions to permit parallel optimum design of structures are outlined.

• 산업공학
• /
• 제9권1호
• /
• pp.41-52
• /
• 1996

As part of effort to reduce the process time from design to manufacture and delivery, the concept of CE(concurrent engineering) has been applied to design process. In this research, the drawing information management system (DIMS) was developed based on CE. The system can distribute electronic documents of drawing or work instruction parallel to all reviewers simultaneously and collect their annotations through network. Mark-up functions are used for annotations on the electronic documents. DIMS is a system which integrates drawing management, engineering BOM, CAD and raster drawings, etc. In this system, a SUN workstation is interfaced with PCs by LAN. CIMCAD-2D, Image Hunter, and ORACLE RDBMS are used for CAD drawings, raster drawings, and drawing information management, respectively. As an integration tool for all the information, LINKAGE is adopted.

• 한국정보통신학회:학술대회논문집
• /
• 한국해양정보통신학회 2005년도 추계종합학술대회
• /
• pp.820-822
• /
• 2005

본 논문에서는 16비트 혹은 32비트 고정 소수점 연산을 지원하는 디지털 신호처리 기능을 강화한 명령어 축소형 마이크로프로세서를 설계하였다. 설계한 마이크로프로세서는 명령어 축소형 마이크로 아키텍쳐의 표준에 따라서 범용 마이크로프로세서의 기능과 디지털 신호처리 프로세서의 기능을 함께 갖추고 있다. 산술연산기능 유닛, 디지털 신호처리 유닛, 메모리 제어 유닛으로 구성되어 있으며, 이 연산 유닛들이 병렬적으로 수행되어 디지털 신호처리 명령이나 로드/스토어 명령어의 지연된 시간을 보상할 수 있게 설계되었다. 이 연산유닛들을 병렬적으로 동작하게 함으로써 5단계 파이프라인의 구조로 고성능 마이크로프로세서를 구현하였다.