• 공학교육연구
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• 제17권2호
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• pp.11-24
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• 2014

The purpose of this study is to develop a teaching-learning model of convergence project based on team teaching. Based on development research methodology which explored a university case, the teaching-learning model was developed including three phases such as preparation, planning, and implementation & evaluation. The preparation phase has three steps as follows: to organize team teaching faculty; to develop convergence projects cooperated by industry and university; and to design instructions based on supporting convergence projects. The last step of preparation phase consists of five design activities of: (1) instructions and teaching contents; (2) communication channel among faculty members; (3) feedback system on students' performance; (4) tools to support learners' activity; and (5) evaluation system. The planning phase has two steps to analyze learners and to introduce and modify instruction and themes of convergence projects. The implementation & evaluation phase includes five steps as bellow: (1) to organize project teams and match teams with faculty members; (2) to do team building and assign duties to students of a team; (3) to provide instruction and consulting to teams; (4) to help teams to conduct projects through creative problem solving; and (5) to design mid-term/final presentation and evaluation. Lastly, the research implications and limitations were discussed for future studies.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.423-424
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• 2008

The procedure of design and verification for a 16-bit RISC processor is introduced in this paper. The proposed processor has Harvard architecture and consists of 24-bit address, 5-stage pipeline instruction execution, and internal debug logic. ADPCM vocoder and SOLA algorithm are successfully carried out on the processor made with FPGA.

• 한국정밀공학회지
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• 제1권2호
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• pp.69-74
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• 1984

In this paper we present a microprocessor-based interpolator using algebraic arithmetic method. The interpolator consists of 2910 "bit-slice" microprocessor chips and 0.5K ROMs of microprogram memory. The system design is an instruction-data-based architecture with 250ns cycle time. A significant feature of the interpolator is that it has flexibility, very fast interpolatioon speed of (max) 250K pulses/sec, and performs additional functions simultaneously. Throughout the paper detailed explanations are given as to how one can design the hardware and software of the interpolator efficently. In addi- tion to hardware and software design, experimental results are pressented.ressented.

• 한국실천공학교육학회논문지
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• 제3권2호
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• pp.142-146
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• 2011

본 논문은 고령친화산업의 활성화를 위한 고령친화산업체에 재직하는 현장인력재교육사업의 사례를 소개한다. 고령친화산업체 재직자를 대상으로 2009년 8월 이후 2년여동안 IT기반 고령친화산업 현장기술인력 재교육사업을 운영하면서 개발된 IT기반의 고령친화제품 개발에 필요한 교과과정을 소개한다. 본 교과과정은 ISD(instruction system design: 교수체제설계) 모형에 기반하여 개발했다. IT기반 고령친화 제품 개발을 위해서 재직자 및 전문가들이 인간공학기반 설계와 IT기반의 설계와 관련된 교육을 요구해서 인간공학기반 제품설계는 "고령친화 인체특성 및 고령자 생활공학", "고령자 색체감성 및 유니버셜디자인", "디자인의 이해 및 디자인 프로세스" 교과목으로 구성되고 고령친화 생활 건강관리기기 설계과정은 "고령친화 IT 기기용 임베디드 시스템 설계 및 디버깅 실습", "고령친화 안드로이드 구현 설계", "실버케어 안드로이드 기반 스마트 장치 설계 및 실습" 교과목으로 구성된다.

• Design & Manufacturing
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• 제16권3호
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• pp.34-38
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• 2022

Regular expression pattern matching is widely used in applications such as computer virus vaccine, NIDS and DNA sequencing analysis. Hardware-based pattern matching is used when high-performance processing is required due to time constraints. ReCPU, SMPU, and REMP, which are processor-based regular expression matching processors, have been proposed to solve the problem of the hardware-based method that requires resynthesis whenever a pattern is updated. However, these processor-based regular expression matching processors inefficiently handle repetitive operations of regular expressions. In this paper, we propose a new instruction set to improve the inefficient repetitive operations of ReCPU and SMPU. We propose REMPi, a regular expression matching processor that enables efficient iterative operations based on the REMP instruction set. REMPi improves the inefficient method of processing a particularly short sub-pattern as a repeat operation OR, and enables processing with a single instruction. In addition, by using a down counter and a counter stack, nested iterative operations are also efficiently processed. REMPi was described with Verilog and synthesized on Intel Stratix IV FPGA.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2008년도 추계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.246-247
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• 2008

Further evolutions of technologies and needs of users will make mobile equipments improved. To make this happen, processor's good performance is essential. Hence, This paper propose a reform of Instruction Execute and Instruction Decode of contemporary ARMv7 which needs low-power and has the high performance for a faster processor. The first chapter explains why the performance of a processor has to be upgraded, the second chapter shows current technologies. The third chapter explains about the proposal and illustrates the structure. Finally, in the forth chapter, the conclusion will be made. 3-way Superscalar, that is proposed in this paper, will make designing a faster processor possible. And it will contribute for the advanced performance of mobile equipments.

• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2014년도 추계학술발표대회
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• pp.53-56
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• 2014

Application specific instruction-set processor (ASIP) is a suitable design choice for system designers who seek both flexibility to handle various applications in the domain together with the performance. Successful development of an ASIP, however, requires a software development kit (SDK) to be provided along with the processor. Synopsys Processor Designer is an ASIP development tool, which takes as input a set of files written in a high-level architecture description language called LISA (Language for Instruction Set Architecture), and generates SDK as well as RTL. Recently, they have added support for the generation of LLVM compiler backend, though some manual work is required. In this paper, we introduce some details in porting LLVM compiler to a custom processor architecture in Synopsys Processor Designer.

• 전자공학회논문지CI
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• 제45권3호
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• pp.142-148
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• 2008

복호된 영상의 블록 경계에서 발생하는 왜곡을 보정하기 위해 사용된 H.264/AVC 표준의 디블록킹 필터는 개선된 품질의 영상을 제공하지만, 이에 사용되는 복잡한 필터링 연산은 복호기의 처리 시간을 지연시키는 주된 요인이 되고 있다. 본 논문에서는 이러한 필터링 연산을 더 빠르게 수행할 수 있는 명령어를 제안하고 ASIP을 구성하여 디블록킹 필터를 가속하였다. LISA를 이용하여 MIPS 기반의 기준 프로세서를 설계하고 디블록킹 필터 모델을 시뮬레이션하여 제안하는 명령어 적용에 따른 실행 사이클의 성능 향상을 비교하였으며, 설계된 기준 프로세서를 CoWare의 Processor Designer를 통해 HDL을 생성하고 Synopsys의 Design Compiler를 이용하여 TSMC 0.25um 공정으로 합성하고 제안하는 명령어를 추가할 경우에 대해 면적 및 동작 지연시간 등을 비교하였다. 합성 결과, 제안하는 명령어 셋을 적용함에 따라 면적 및 동작 지연시간에서 각각 7.5%와 3.2%의 증가를 보였으며, 이로 인해 실행 사이클 면에서는 평균 18.18%의 성능 향상을 보였다.

• IEIE Transactions on Smart Processing and Computing
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• 제4권5호
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• pp.366-370
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• 2015

This paper proposes a method for improving a branch predictor for the extendable instruction set computer (EISC) processor. The original EISC branch predictor has several shortcomings: a small branch target buffer, absence of a global history, a one-bit local branch history, and unsupported prediction of branches following LERI, which is a special instruction to extend an immediate value. We adopt a G-share branch predictor and eliminate the existing shortcomings. We verified the new branch predictor on a field-programmable gate array with the Dhrystone benchmark. The newly proposed EISC branch predictor also accomplishes higher branch prediction accuracy than a conventional branch predictor.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1991년도 한국자동제어학술회의논문집(국제학술편); KOEX, Seoul; 22-24 Oct. 1991
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• pp.1633-1638
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• 1991

A CAI system is developed to support the Instruction of an aircraft conceptual design for aeronautical engineering students. Three system concepts are proposed and an Object-Oriented approach is applied to construct the system. The system has three major functions to perform a conceptual design: (1) the system stores modular data and empirical formulas used for a wide range of aircraft design tasks from light aircraft to long range airliners. (2) Implementation of modules by message passing makes it easy to realize the various design tasks required for different design requirements. (3) The system allows users to study trade-off among the requirements. The system has a graphical user Interface which allows users to communicate with the system interactively. The effectiveness of the system Is demonstrated through some case studies.