• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.649-652
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• 2013

LEON3 is a 32-bit synthesisable processor based on the SPARC V8. It can be connected to AMBA 2.0 bus and has a 7-stage pipeline, IEEE-754 FPU and 256[KB] cache. It can be easily implemented using FPGA and used for a SoC design. DSU which comes with LEON3 can be used to control and monitor the operation of LEON3. And DSU makes it easy to set a debugging environment for the development of both hardware and software for an embedded systems based on LEON3. This paper presents the summary of the development of LEON3 monitoring software.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.7
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• pp.1332-1339
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• 2001

SoC(System on Chip) technology is widely used in the field of embedded systems by providing high flexibility for a specific application domain. An important aspect of development any new embedded system is verification which usually requires lengthy software and hardware co-design. To reduce development cost of design effort, the instruction set of microprocessor must be suitable for a high level language compiler. And FPGA prototype system could be derived and tested for design verification. In this paper, we propose a 16 bit FPGA microprocessor, which is tentatively-named EISC16, based on an EISC(Extendable Instruction Set Computer) architecture for embedded applications. The proposed EISC16 has a 16 bit fixed length instruction set which has the short length offset and small immediate operand. A 16 bit offset and immediate operand could be extended using by an extension register and an extension flag. We developed a cross C/C++ compiler and development software of the EISC16 by porting GNU on an IBM-PC and SUN workstation and compared the object code size created after compiling a C/C. standard library, concluding that EISC16 exhibits a higher code density than existing 16 microprocessors. The proposed EISC16 requires approximately 6,000 gates when designed and synthesized with RTL level VHDL at Xilinix's Virtex XCV300 FPGA. And we design a test board which consists of EISC16 ROM, RAM, LED/LCD panel, periodic timer, input key pad and RS-232C controller. 11 works normally at 7MHz Clock.

• Proceedings of the Korea Information Processing Society Conference
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• 2008.11a
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• pp.843-845
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• 2008

CE (Consumer Electronics) 시장에서 Embedded System 은 time-to-market 이라는 개념이 나날이 중요해 지고 있다. 시스템의 중심인 core processor 에 대하여 지원하는 여러 가지 software toolkit 의 빠른 개발은 무엇보다 중요해지고 있다. 이 논문에서는 GNU Binutils 를 기반으로 ADL 을 이용하여 Embedded system의 core processor 를 위하여 신속한 Assembler 와 Linker 를 개발하는 플랫폼을 개발하였다. 이 플랫폼은 서울대학교 소프트웨어 최적화 연구실에서 개발한 ADL (Architecture Description Language)[1] 을 이용하여 core processor 를 기술하면 자동으로 Assembler 와 Link 를 생성해주는 시스템이다.

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.532-535
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• 2004

Architecture generation is the first step in the design of software systems. Most of the qualities that the final software system possesses are usually decided at the architecture development stage itself. Thus, if the final system should be usable, testable, secure, high performance, mobile and adaptable, then these qualities or non­functional requirements should be engineered into the architecture itself. In particular, adaptability is emerging as an important attribute required by almost all software systems. The machinery and tools in the remote site surveillance and connects intelligence information machinery and tools at Internet. We need the server which uses different embedded operating system to become private use. With the progress of information-oriented society, many device with advanced technologies invented by many companies. However, the current firmware technologies have many problems to meet such high level of new technologies. In this paper, we have successfully ported linux on an embedded system, which is based on intel StrongARM SA-1 1 10 processor, then written several network modules for internet-based network devices.

• Spatial Information Research
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• v.10 no.4
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• pp.551-565
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• 2002

To carry out systematic groundwater assessment, exploration and management and to use these for protection of optimal groundwater yield, a data analysis and management system is required. Thus, the object of this research was to develop and apply software that integrates GIS and groundwater modeling: GISGAM (GIS for groundwater analysis and management system). The GIS program ArcView and the groundwater-modeling program MODFLOW were used for the GISGAM. The program components consist of a pre-processor, a processor, and a post-processor for groundwater modeling. In addition, GIS functions such as input, manipulation, analysis and output of data were embedded into the program. In applying the program to pilot area, topography, geology, soil, land use and well databases, and a groundwater flow model were constructed for the study area. This case study revealed the advantage and convenience of groundwater modeling using GIS capabilities. By integrating GIS and the groundwater model, the impact of changing values of hydrogeological constants on model results could be more easily evaluated.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.6 no.4
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• pp.315-324
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• 2005

VOD(video on demand) is a video service by users' order, that is, a video service on demand. That means the users can select and watch the video content that has been saved on sewer, out of broadcasting in the usual process like TV. At present the client of VOD system bases on PC. As the PC-based client uses the software MPEG decoder, the main processor specification has an effect on the capacity. Also people, who don't know how to use their PC, cannot be provided the VOD service. The purpose of this paper is to show the process of the development the VOD client system Into the embedded type with hardware MPEG-4 decoder. The main processor is the SC1200 of x86 Family in National Semiconductor with a built-in video processor and the memory is 128Mbyte SDRAM. Also, in order that the VOD service can be provided using the Internet, the Ethernet controller is included. As the hardware MPEG-4 decoder is used in the embedded VOD client system, which is developed, it can make the low capacity of the main processor. Therefore it is able to be developed as a low-price system. The embedded VOD client system is easy for anyone to control easily with the remote control and can be played through TV.

• Journal of Institute of Control, Robotics and Systems
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• v.20 no.4
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• pp.474-479
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• 2014

LEON3 is a 32-bit synthesizable processor based on the SPARC V8. It can be connected to AMBA 2.0 bus and has a 7- stage pipeline, IEEE-754 FPU and 256[KB] cache. It can be easily implemented using FPGA and used for a SoC design. DSU which comes with LEON3 can be used to control and monitor the operation of LEON3. And DSU makes it easy to set a debugging environment for the development of both hardware and software for an embedded systems based on LEON3. This paper presents the summary of the debugging tool for LEON3 based embedded systems. The debugging tool can initialize the target hardware, find out how the target hardware is configured, load application code to a specified memory space and run that application code. To provide users a debugging environment, it can set breakpoints and control the operation of LEON3 correspondingly. And function call trace is one of key functions of the debugging tool.

• Journal of the Korean Institute of Intelligent Systems
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• v.20 no.4
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• pp.580-585
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• 2010

In this paper, The object Tracking System is designed by SOPC based Nios II embedded processor and C2H compiler. And this system using single PTZ camera can effectively control IPs in the platform of SOPC based Nios II Embedded Processor and creating IP by C2H(C-To-Hardware) compiler for image-in/output, image-processing and devices of communication that can supply various monitoring information to network or serial. Accordingly, Special quality and processing speed of object tracking using high-quality algorism in the system is improved by hardware/software programming methods.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.6
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• pp.1086-1090
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• 2004

Architecture generation is the first step in the design of software systems. Most of the qualities that the final software system possesses are usually decided at the architecture development stage itself. Thus, if the final system should be usable, testable, secure, high performance, mobile and adaptable, then these qualities or non-functional requirements should be engineered into the architecture itself. In particular, adaptability is emerging as an important attribute required by almost all software systems. The machinery and tools in the remote site surveillance and connects intelligence information machinery and tools at Internet. We need the server which uses different embedded operating system to become private use. With the progress of information-oriented society, many device with advanced technologies invented by many companies. However, the current firmware technologies have many problems to meet such high level of new technologies. In this paper, we have successfully ported linux on an embedded system, which is based on intel Strong ARM SA-1110 processor, then written several network modules for internet-based network devices.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.50-61
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• 2010

Nowadays, the SoC is watched by all over the world with interest. The design trend of the SoC is hardware and software co-design which includes the design of hardware structure in RTL level and the development of embedded software. Also the technology is toward deep-submicron and the observability of the SoC's internal state is not easy. Because of the above reasons, the SoC debug is very difficult and time-consuming. So we need a reliable debugger to find the bugs in the SoC and embedded software. In this paper, we developed a hardware debugger named OCD. It is based on IEEE 1140.1 JTAG standard. In order to verify the operation of OCD, it is integrated into the 32bit RISC processor - Core-A (Core-A is the unique embedded processor designed by Korea) and is tested by interconnecting with software debugger. When embedding the OCD in Core-A, there is 14.7% gate count overhead. We can modify the DCU which occupies 2% gate count in OCD to adapt with other processors as a debugger.