• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.1
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• pp.28-35
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• 2007

This paper presents a high-speed flash analog-to-digital converter (ADC) for ultra wide band (UWB) receivers. In this flash ADC, the interpolating technique is adopted to reduce the number of the amplifiers and a linear and wide-bandwidth interpolating amplifier is presented. For this ADC, the transistor size for the cascaded stages is inversely scaled to improve the trade-off in bandwidth and power consumption. The active inductor peaking technique is also employed in the pre-amplifiers of comparators and the track-and-hold circuit to enhance the bandwidth. Furthermore, a digital-to-analog converter (DAC) is embedded for the sake of measurements. This chip has been fabricated in $0.13{\mu}m$ 1P8M CMOS process and the total power consumption is 113mW with 1V supply voltage. The ADC achieves 4-bit effective number of bits (ENOB) for input signal of 200MHz at 5-GSample/sec.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.10 no.1
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• pp.70-77
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• 1999

A miniaturized voltage controlled oscillator using multi-layer ceramic technology at PCS frequency band is designed and fabricated. To improve the phase noise characteristics and to reduce the size, the strip line which is embedded in a high performance multi-layer ceramic substrate is used as an inductor of VCO. And the fabricated VCO is very small size ($6mm\times6mm\times2mm$). At the bias condition of 3.3 V and 9mA, the output power and phase noise in the operating frequency range of 1,720~1,780 MHz are -3.7 dBm and -95 dBc/Hz at 10 KHz offset from the carrier, respectively. The phase noise and size are better than the conventional VCO using glass epoxy substrate.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.25 no.8
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• pp.8-19
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• 2011

This paper was compared for the output voltage and efficiency of the single-phase Z-source inverter(ZSI) according to shoot through duty ratio D. The eight single-phase ZSI in this study are typical ZSI, Embedded ZSI(EZSI), Improved ZSI(IZSI), Quasi ZSI(QZSI), Series ZSI, Trans ZSI(TSI), Switched inductor ZSI(SL-ZSI) and Extended boost ZSI (exZSI). The eight ZSI are divided into two Groups. ; Group-1 which is ZSI with the ordinary voltage boost factor B, and Group-2 which is ZSI with the maximum voltage boost factor B. For the execution of the proposed study, the PSIM simulation was achieved under the condition of input DC voltage=150[V] of ZSI, load =30[${\Omega}$] and 60[Hz] output filter. The output voltage and efficiency of each ZSI were calculated within the limits of D=0.1~0.4. As a result, the output peak voltage of Group-2 was suddenly increased in a specified duty ratio D, and its efficiency was rapidly decreased. On the contrary, Group-1 shown the output and efficiency characteristics without sudden change compared to Group-2 despite the duty ratio increase. The efficiency of the Group-2 was sharply declined at duty ratio D of the most output voltage, but, in case of Group-1, the efficiency was slightly declined. Finally, the input DC current of ZSI with DCM and CCM was discussed.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.4
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• pp.362-370
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• 2010

In this paper, a compact RF Front-end module for Wireless Fidelity(Wi-Fi) and Worldwide Interoperability for Microwave Access(WiMAX) applications is realized by low temperature co-fired ceramic(LTCC) technology. The RF Front-end module is composed of three LTCC band-pass filters, a Film Bulk Acoustic Resonator(FBAR) filter, fully embedded matching circuits, an SPDT switch for mode selection, an SPDT switch for Tx/Rx selection, and an SP4T switch for band selection. The parasitic elements of 0.2~0.3 pF are generated by the structure of stacking in the top pad pattern for DC block capacitor of SPDT switch for mode selection. These kinds of parasitic elements break the matching characteristic, and thus, the overall electrical performance of the module is degraded. In order to compensate it, we insert a parallel lumped-element inductor on capacitor pad pattern for DC block, so that we obtain the optimized performance of the RF Front-end module. The fabricated RF front-end module has 12 layers including three inner grounds and it occupies less than $6.0mm{\times}6.0mm{\times}0.728mm$.