• Journal of Broadcast Engineering
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• v.21 no.5
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• pp.792-802
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• 2016

Real time verification is necessary, since there are several features that cannot be verified through design simulation in the design of multiband soundbar system. And then this paper describes an implementation of an FPGA-based real-time verification system for a soundbar SoC with an embedded processor. It is verified a real-time performance test and a listening test which are several features in the design stage that cannot be verified through a design simulation. The measurement of quantitative specifications such as SNR, THD+N, frequency response, etc. as well as the listening test were performed through the implemented FPGA system, and it was verified that test results satisfied the target specifications.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.3
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• pp.437-443
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• 2007

In this paper, we propose the power-aware test framework for Network-on-Chip, which is based on embedded processor and on-chip network. First, the possibility of using embedded processor and on-chip network isintroduced and evaluated with benchmark system to test the other embeddedcores. And second, a new generation method of test pattern is presented to reduce the power consumption of on-chip network, which is called don't care mapping. The experimental results show that the embedded processor can be executed like the automatic test equipments, and the test time is reduced and the power consumption is reduced up to 8% at the communication components.

• Journal of the Korea Society of Computer and Information
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• v.21 no.9
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• pp.1-9
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• 2016

Recent embedded processors employ set-associative L1 instruction cache to improve the performance. The energy consumption in the set-associative L1 instruction cache accounts for considerable portion in the embedded processor. When an instruction is required from the processor, all ways in the set-associative instruction cache are accessed in parallel. In this paper, we propose the technique to reduce the energy consumption in the set-associative L1 instruction cache effectively by accessing only one way. Gshare branch predictor is employed to predict the instruction flow and determine the way to fetch the instruction. When the branch prediction is untaken, next instruction in a sequential order can be fetched from the instruction cache by accessing only one way. According to our simulations with SPEC2006 benchmarks, the proposed technique requires negligible hardware overhead and shows 20% energy reduction on average in 4-way L1 instruction cache.

• IEMEK Journal of Embedded Systems and Applications
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• v.16 no.6
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• pp.299-305
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• 2021

Dissolved oxygen, pH, and temperature are the most important factors for fish farming because they affect fish growth and mass mortality of the fish. Therefore, fish farm workers must always check all pools on the farm, but this is very difficult in reality. That's why we developed a control system for smart fish farms. This system includes a gateway, sensor gatherers, and a PC program using LabVIEW. One sensor gatherer can cover up to four pools. The sensor gatherers are connected to the gateway in the form of a bus. For the gateway, the ATmega2560 is used as the main processor for communication and the STM32F429 is used as a sub-processor for displaying LCD. For the sensor gatherer, ATmega2560 is used as the main processor for communication. MQTT (Message Queuing Telemetry Transport), RS-485, and Zigbee are used as the communication protocols in the control system. The users can control the temperature and the dissolved oxygen using the PC program. The commands are transferred from the PC program to the gateway through the MQTT protocol. When the gateway gets the commands, it transfers the commands to the appropriate sensor gatherer through RS-485 and Zigbee.

• Journal of Internet Computing and Services
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• v.21 no.5
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• pp.149-157
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• 2020

Recently, as interest in artificial intelligence has increased, many studies have been conducted to implement AI processors. However, the AI processor requires functional verification as well as performance verification on whether the AI processor is suitable for the application. In this paper, We propose an AI processor performance analyzer that can verify the application performance and explore the limitations of the processor. By Using the performance analyzer, we explore the limitations of the AI processor and optimize the AI model to fit an AI processor in image recognition and speech recognition applications.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.4A
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• pp.447-457
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• 2004

This paper proposes a RSA crypto-processor for embedded systems. The architecture of the RSA crypto-processor should be used relying on Big Montgomery algorithm, and is supported by configurable bit size. The RSA crypto-processor includes a RSA control signal generator, an optimal Big Montgomery processor(adder, multiplier). We use diverse arithmetic unit (adder, multiplier) algorithm. After we compared the various results, we selected the optimal arithmetic unit which can be connected with ARM core-processor. The RSA crypto-processor was implemented with Verilog HDL with top-down methodology, and it was verified by C language and Cadence Verilog-XL. The verified models were synthesized with a Hynix 0.25${\mu}{\textrm}{m}$, CMOS standard cell library while using Synopsys Design Compiler. The RSA crypto-processor can operate at a clock speed of 51 MHz in this worst case conditions of 2.7V, 10$0^{\circ}C$ and has about 36,639 gates.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.1
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• pp.233-238
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• 2016

Recently, the multi-core processor architecture is widely adopted in the embedded processors for enhancing its performance. Multi-core processors are classified either as symmetric or asymmetric. Asymmetric multicore processors are known to score higher performance and more efficient than symmetric multi-core processors. In order to study the performance enhancement of asymmetric multi-core embedded processors over the symmetric ones, the trace-driven simulation has been executed for various asymmetric embedded dual-core, quad-core, octa-core and hexadeca-core processors and compared with the symmetric ones of similar hardware budget using MiBench benchmarks as input.

• ETRI Journal
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• v.31 no.6
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• pp.732-740
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• 2009

This paper describes the implementation of a digital audio effect system-on-a-chip (SoC), which integrates an embedded digital signal processor (DSP) core, audio codec intellectual property, a number of peripheral blocks, and various audio effect algorithms. The audio effect SoC is developed using a software and hardware co-design method. In the design of the SoC, the embedded DSP and some dedicated hardware blocks are developed as a hardware design, while the audio effect algorithms are realized using a software centric method. Most of the audio effect algorithms are implemented using a C code with primitive functions that run on the embedded DSP, while the equalization effect, which requires a large amount of computation, is implemented using a dedicated hardware block with high flexibility. For the optimized implementation of audio effects, we exploit the primitive functions of the embedded DSP compiler, which is a very efficient way to reduce the code size and computation. The audio effect SoC was fabricated using a 0.18 ${\mu}m$ CMOS process and evaluated successfully on a real-time test board.

• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.166-168
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• 2007

This paper is dealing with how to control of a client robot's movement for instructions from a server PC and a wireless andremote control Robot that sends the server information of images for monitoring. To implement this. 802.11x WLAN with TCP/IP socket programming is used to get the driving instructions from the server PC and control movements of the robot such as a forward, backward and directions. As well as this, ARM9 cored PAX255 embedded processor and Linux OS is used for the function transmitting BMP format of 320 ${\times}$ 240 pixel for stopped image data.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.243-246
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• 2003

The design of router that converts IP packets from IPv4 network to IPv6 network using embedded Linux toolkit based on processor is presented. As an address transition platform, IPv6 module is transplanted to Linux using processor and the experiment was done with IPv4 and IPv6. In order to build the test network, it is constructed with Tunneling mechanism of IPv4 and IPv6 network. The packet value is obtained about 2$\mu$sec on average a 2 hops on the ICMP ping6.