• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1976-1981
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• 2003

Except a desktop computer and workstation, an embedded system is a system containing microprocessors. While a desktop computer and a workstation are designed for a general purpose, an embedded system is designed for a dedicated purpose. Thus, an embedded system must meet some constraints such as low power consumption, low cost, small size, real-time, or user-defined ones. A simple and low cost embedded system may be able to be designed without using embedded operating systems (OS). However, considered design time and effort, some embedded system had better be designed with using embedded OS. Under given constraints and purpose of some embedded systems, one embedded OS can save more time, cost, and effort in designing those embedded systems than others. This paper compares four embedded OSs, Windows CE, Embedded Linux, pSOS, and uC/OS. It analyzes several issues of embedded OS such as process scheduling, inter-process communication (IPC), memory management, and network support. Also, it describes the product of each embedded OS.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.10
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• pp.2059-2063
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• 2009

This paper presents a programmable System-On-a-chip (SoC) for various embedded smart applications that need Neural Network computations. The system is fully implemented into a prototyping platform based on Field Programmable Gate Array (FPGA). The SoC consists of an embedded processor core and a reconfigurable hardware accelerator for neural computations. The performance of the SoC is evaluated using a real image processing application, an optical character recognition (OCR) system.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2012.05a
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• pp.319-320
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• 2012

• IEMEK Journal of Embedded Systems and Applications
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• v.7 no.6
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• pp.331-338
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• 2012

This paper presents a wireless sensor network protocol aimed for artificial structure monitoring. The proposed protocol enables the sensor network to operate at a low duty cycle for reducing power consumption with a high degree of synchronization accuracy. It also enables event-triggered measurement of environmental information with a high sampling rate and the transmission of the measured data with a low latency. The feasibility of the proposed protocol is demonstrated through experiments involving three sensor nodes and a sink node. Though a tunnel health monitoring was considered in the paper, the proposed protocol can be easily adopted in other areas.

• IEMEK Journal of Embedded Systems and Applications
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• v.15 no.5
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• pp.261-268
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• 2020

Genetic algorithms find the optimal solution by mimicking the evolution of natural organisms. In this study, the genetic algorithm was used to enable Pac-Man's reinforcement learning, and a simulator to observe the evolutionary process was implemented. The purpose of this paper is to reinforce the learning of the Pacman AI of the simulator, and utilize genetic algorithm and artificial neural network as the method. In particular, by building a low-power artificial neural network and applying it to a genetic algorithm, it was intended to increase the possibility of implementation in a low-power embedded system.

• Journal of Technology Innovation
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• v.14 no.2
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• pp.143-165
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• 2006

By analyzing five in-depth case studies of suppliers in newly emerging Vietnam's motorcycle industry, this paper explores the differences in patterns and processes of capability improvement of suppliers who participate in different kinds of supplier-assembler network with different structures. The paper finds the correlation between the kinds of suppliers' capabilities improved and the structure of networks they participate in. While suppliers in arm-length networks can improve more upstream capabilities (structure design, process desist), suppliers in embedded networks can improve more downstream capabilities (process design, process setup, process maintenance and delivery control). Two capability improvement patterns of firms in newly emerging economy are indicated. The first pattern is asymmetrical improvement, either upstream or downstream capabilities, by participating in either arm-length or embedded networks. This pattern obstructs the suppliers to meet the requirements of new buyers rho come from different kinds of network. The second pattern is symmetrical improvement by joining both arm-length and embedded networks.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.243-246
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• 2003

The design of router that converts IP packets from IPv4 network to IPv6 network using embedded Linux toolkit based on processor is presented. As an address transition platform, IPv6 module is transplanted to Linux using processor and the experiment was done with IPv4 and IPv6. In order to build the test network, it is constructed with Tunneling mechanism of IPv4 and IPv6 network. The packet value is obtained about 2$\mu$sec on average a 2 hops on the ICMP ping6.

• IEMEK Journal of Embedded Systems and Applications
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• v.6 no.4
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• pp.231-241
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• 2011

Recently, system virtualization has been applied to consumer electronics (CE) such as smart mobile phones. Although multi-core processors have become a viable solution for complex applications of consumer electronics, the issue of utilizing multi-core resources in the virtualization layer has not been researched sufficiently. In this paper, we present a new hypervisor design and implementation for multi-core CE devices. We concretely describe virtualization methods for a multi-core processor and multi-core-related subsystems. We also analyze bottlenecks of network performance in a virtualization environment that supports multimedia applications and propose an efficient virtual interrupt distributor. Our new multi-core hypervisor improves network performance by 5.5 times as compared to a hypervisor without the virtual interrupt distributor.

• The KIPS Transactions:PartA
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• v.17A no.4
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• pp.181-188
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• 2010

In this study, we suggest the system to analyze network users' action patterns by using Data-Mining Technique. We installed Network Tap to implement the analysis system of network action and copied the network packet. The copied packet is stored at the database through MainMemoryDB(MMDB) of the high-speed. The stored data analyze the users' action patterns by using Data-Mining Technique and then report the results to the network manager on real-time. Also, we applied the standard XML document exchange method to share the data between different systems. We propose this action pattern analysis system operated embedded type of SetToBox to install easily and support low price.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.3
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• pp.437-443
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• 2007

In this paper, we propose the power-aware test framework for Network-on-Chip, which is based on embedded processor and on-chip network. First, the possibility of using embedded processor and on-chip network isintroduced and evaluated with benchmark system to test the other embeddedcores. And second, a new generation method of test pattern is presented to reduce the power consumption of on-chip network, which is called don't care mapping. The experimental results show that the embedded processor can be executed like the automatic test equipments, and the test time is reduced and the power consumption is reduced up to 8% at the communication components.