• Annual Conference of KIPS
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• 2013.11a
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• pp.46-47
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• 2013

지난 수십년 동안 휴대기기 시장의 다양한 요구에 맞추어 임베디드 시스템 기술이 발전되어 왔다. 현재의 임베디드 시스템은 작은 크기의 특화된 하드웨어를 차용하면서도 높은 효율의 성능을 저가에 제공할 수 있는 기술들이 핵심을 이루고 있다. 이러한 핵심 기술들 중의 하나가 다중 메모리 뱅크이다. 예를 들면, 이중 메모리 뱅크는 같은 공간에 두 배의 메모리 대역폭의 제공할 수 있는 특징을 갖는다. 이러한 특징은 이중포트 메모리에 비하여 적은 비용으로 동일한 대역폭을 제공할 수 있는 장점을 제공한다. 그러나 현재까지도 다중 메모리 뱅크의 효율적인 사용을 지원하는 소프트웨어 기술은 부족한 실정이다. 본 연구에서는 다중 메모리 뱅크의 활용 문제를 간섭 그래프 (interference graph)를 이용하여 효과적으로 해결하였다.

• Annual Conference of KIPS
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• 2010.11a
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• pp.1599-1602
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• 2010

가상화 기법은 PDA, 스마트 폰과 같은 임베디드 시스템에서 다양한 운영체제와 응용 프로그램들을 제공할 수 있게 한다. 그러나 임베디드 시스템은 매우 제한된 컴퓨팅 자원을 갖고 있기 때문에 많은 수의 가상 머신을 동작하기 어렵다. 특히, 프로세스 동작에 필수적인 메모리 공간의 부족은 반드시 해결되어야 하는 문제이다. 데스크탑과 같은 시스템은 페이지 스왑을 통해 이를 해결하지만, 디스크가 없는 임베디드 시스템은 해결이 쉽지 않다. 본 논문은 메모리 공간 부족 문제를 해결하기 위해 불필요한 메모리 공간의 압축을 이용한 여유 공간의 추가 확보 기법을 제안한다. 페이지 압축을 통해 페이지 스왑하는 것과 유사한 효과를 얻을 수 있게 한다. 이는 가상화로 인한 메모리 분할과 불필요한 프로세스의 메모리 상주 등의 이유로 인한 임베디드 시스템 가상화 환경에서의 메모리 부족 문제를 해결할 수 있다. 본 논문은 기능 구현에 앞서 임베디드 시스템과 가상화 환경에 맞춘 메모리 압축 스왑 기법을 디자인한다.

• Annual Conference of KIPS
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• 2011.04a
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• pp.27-29
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• 2011

위성 전체 시스템의 동작과 임무 수행을 책임지고 있는 위성 탑재 소프트웨어의 개발 과정에서 위성 탑재 컴퓨터를 이해하고 소프트웨어가 동작하기 위한 환경을 구성하는 작업은 필수적인 과정이다. 위성 탑재 소프트웨어 개발의 초기 과정은 하드웨어와 매우 밀접하게 관련되어 있으며, 이러한 하드웨어의 동작을 보다 쉽게 테스트하기 위한 환경이 필요하게 된다. 최근 위성 탑재 컴퓨터로 널리 쓰이고 있는 LEON 2/3 플랫폼은 AHB-UART 를 이용하여 Memory 에 대한 직접적인 R/W Operation 을 지원하고 있는데, 본 논문에서는 이 기능을 이용하여 위성 탑재 컴퓨터를 보다 쉽게 테스트할 수 있는 테스트 스크립트 언어의 구현 방안에 대하여 기술하며, 더불어 이러한 테스트 언어의 구현에 있어 ANTLR 을 이용하는 방안도 함께 소개한다.

• Nuclear Engineering and Technology
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• v.55 no.2
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• pp.443-451
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• 2023

Machine Learning has introduced many solutions in data science, but its application in IoT faces significant challenges, due to the limitations in memory size and processing capability of constrained devices. In this paper we design an automatic gamma radiation detection and identification embedded system that exploits the power of TinyML in a SiPM micro radiation sensor leveraging the Edge Impulse platform. The model is trained using real gamma source data enhanced by software augmentation algorithms. Tests show high accuracy in real time processing. This design has promising applications in general-purpose radiation detection and identification, nuclear safety, medical diagnosis and it is also amenable for deployment in small satellites.

• Journal of KIISE:Computer Systems and Theory
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• v.37 no.5
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• pp.292-303
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• 2010

On-chip cache memories play an important role in both performance and energy consumption points of view in resource-constrained embedded systems by filtering many off-chip memory accesses. We propose a 2-level data cache architecture with a low energy-delay product tailored for the embedded systems. The L1 data cache is small and direct-mapped, and employs a write-through policy. In contrast, the L2 data cache is set-associative and adopts a write-back policy. Consequently, the L1 data cache is accessed in one cycle and is able to provide high cache bandwidth while the L2 data cache is effective in reducing global miss rate. To reduce the penalty of high miss rate caused by the small L1 cache and power consumption of address generation, we propose an ECP(Early Cache hit Predictor) scheme. The ECP predicts if the L1 cache has the requested data using both fast address generation and L1 cache hit prediction. To reduce high energy cost of accessing the L2 data cache due to heavy write-through traffic from the write buffer laid between the two cache levels, we propose a one-way write scheme. From our simulation-based experiments using a cycle-accurate simulator and embedded benchmarks, the proposed 2-level data cache architecture shows average 3.6% and 50% improvements in overall system performance and the data cache energy consumption.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.9
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• pp.691-698
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• 2006

TCP/IP Offload Engine (TOE) is a technology that processes TCP/IP on a network adapter instead of a host CPU to reduce protocol processing overhead from the host CPU. There have been some approaches to implementing TOE: software TOE based on an embedded processor; hardware TOE based on ASIC implementation; and hybrid TOE in which software and hardware functions are combined. In this paper, we designed software modules and hardware modules for a hybrid TOE on an FPGA that had two processor cores. Software modules are based on the embedded Linux. Hardware modules are for data transmission (TX) and reception (RX). One core controls the TX path and the other controls the RX path of the Linux. This TX/RX path separation mechanism can reduce task switching overheads between processes and overcome poor performance of single embedded processor. Hardware modules deal with creating headers for outgoing packets, processing headers of incoming packets, and fetching or storing data from or to the host memory by DMA. These can make it possible to improve the performance of data transmission and reception. We proved performance of the TOE with separated transmission and reception paths by performing experiments with a TOE network adapter that was equipped with the FPGA having processor cores.

• The KIPS Transactions:PartD
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• v.11D no.2
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• pp.443-452
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• 2004

The paper presents an intelligent space management system for ubiquitous computing. The system is basically a home/office automation system that could control light, electronic key, and home appliances such as TV and audio. On top of these basic capabilities, there are four elegant features in the system. First, we can access the system using either a cellular Phone or using a browser on the PC connected to the Internet, so that we control the system at any time and any place. Second, to provide more human-oriented interface, we integrate voice recognition functionalities into the system. Third, the system supports not only reactive services but also proactive services, based on the regularities of user behavior. Finally, by exploiting embedded technologies, the system could be run on the hardware that has less-processing power and storage. We have implemented the system on the embedded board consisting of StrongARM CPU with 205MHz, 32MB SDRAM, 16MB NOR-type flash memory, and Relay box. Under these hardware platforms, software components such as embedded Linux, HTK voice recognition tools, GoAhead Web Server, and GPIO driver are cooperated to support user-friendly intelligent space.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.46 no.4
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• pp.21-30
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• 2009

Fusion flash memory such as OneNAND$^{TM}$ is popular as a ubiquitous storage device for embedded systems because it has advantages of NAND and NOR flash memory that it can support large capacity, fast read/write performance and XIP(eXecute-In-Place). Besides, OneNAND$^{TM}$ provides not only advantages of hybrid structure but also multi-block erase function that improves slow erase performance by erasing the multiple blocks simultaneously. But traditional NAND Flash Translation Layer may not fully support it because the garbage collection of traditional FTL only considers a few block as victim block and erases them. In this paper, we propose an Erase Group Flash Translation Layer for improving multi-block erase function. EGFTL uses a superblock scheme for enhancing garbage collection performance and invalid block management to erase multiple blocks simultaneously. Also, it uses clustered hash table to improve the address translation performance of the superblock scheme. The experimental results show that the garbage collection performance of EGFTL is 30% higher than those of traditional FTLs, and the address translation performance of EGFTL is 5% higher than that of Superblock scheme.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.4
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• pp.43-54
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• 2007

This paper presents design and verification of a face detection hardware for real time application. Face detection algorithm detects rough face position based on already acquired feature parameter data. The hardware is composed of five main modules: Integral Image Calculator, Feature Coordinate Calculator, Feature Difference Calculator, Cascade Calculator, and Window Detection. It also includes on-chip Integral Image memory and Feature Parameter memory. The face detection hardware was verified by using S3C2440A CPU of Samsung Electronics, Virtex4LX100 FPGA of Xilinx, and a CCD Camera module. Our design uses 3,251 LUTs of Xilinx FPGA and takes about 1.96${\sim}$0.13 sec for face detection depending on sliding-window step size, when synthesized for Virtex4LX100 FPGA. When synthesized on Magnachip 0.25um ASIC library, it uses about 410,000 gates (Combinational area about 345,000 gates, Noncombinational area about 65,000 gates) and takes less than 0.5 sec for face realtime detection. This size and performance shows that it is adequate to use for embedded system applications. It has been fabricated as a real chip as a part of XF1201 chip and proven to work.

• Journal of Advanced Navigation Technology
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• v.11 no.3
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• pp.239-251
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• 2007

This thesis is about the reduction of the power consumption in GPS embedded terminals with periodic position fix to improve the time delay of position determination. In order to improve time delay of position determination during the wireless terminal is powered on, it needs to be set such that it can be periodically recalibrated by the GPS and those recalibrated values need to be saved in the terminal's memory so that it can reduce the time delay from the request of location. By using the trace of the information that's been saved in the terminal's memory, it can be set so that it'll be easier to determine whether the wireless terminal has gone into buildings and have the capability of checking if it has gone into a specific building. Likewise, while the terminal is turned on, in order calibrate the location, it needs to continuously work the GPS engine which leads to a rapid decrease in terminal's idle time. This thesis proposes some solutions regarding these issues - reducing 20 ~ 30% of the battery consumption for GPS visible situation that can occur when the wireless terminal periodically calibrates its location to determine the in-building status, and extending the idle time of the terminal by flexibly using the suggested GPS calibration time method according to wireless terminal's mobility.