• Title/Summary/Keyword: Embedded Memory

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Design of a Max CID Assignable AAL2 Switch (최대 CID를 지정할 수 있는 AAL2 스위치의 설계)

  • 양승엽;이정승;김장복
    • Proceedings of the IEEK Conference
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    • 1999.11a
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    • pp.113-116
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    • 1999
  • This paper presents a hardware architecture of AAL(ATM Adaptation Layer) type 2 switch. The proposed architecture can assign and configure maximum AAL2 CID limit. AAL2 is the protocol which has been recommended by ITU-T and ATM-Forum for low bit rate delay sensitive services. The architecture assumes 155 Mbps STM-1/STS-3c physical interface, maximum VCC can be 64K connections. It can support maximum 16,384M AAL2 connections. For efficient use of peripheral memory, a concept of segment address was proposed. The proposed AAL2 switch hardware architecture can be used in ATM network as a standalone server or embedded module in a ATM switching system.

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An Analysis of Random Built-In Self Test Techniques for Embedded Memory Chips (내장된 메모리 테스트를 위한 랜덤 BIST의 비교분석)

  • 김태형;윤수문;김국환;박성주
    • Proceedings of the IEEK Conference
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    • 1999.11a
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    • pp.935-938
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    • 1999
  • 메모리 테스트는 Built-In Self Test(BIST)와 같이 메모리에 내장된 회로를 통하여 자체 점검하는 방법과 테스터를 통하여 생성된 패턴을 주입하는 방법이 있다. 테스트 패턴 생성방법으로는 각각의 고장모델에 대한 테스트 패턴을 deterministic하게 생성해주는 방법과 Pseudo Random Pattern Generator(PRPG)를 이용하여 생성하는 경우로 구분할 수 있다. 본 연구에서는 PRPG를 패턴 생성기로 사용하여 여러 가지 메모리의 결함을 대표한다고 볼 수 있는 Static 및 Dynamic Neighborhood Pattern Sensitive Fault(NPSF) 등 다양한 종류의 고장을 점검할 수 있도록 메모리 BIST를 구성하였다. 기존의 Linear Feedback Shift Register(LFSR)보다 본 연구에서 제안하는 Linear Hybrid Cellular Automata(LHCA)를 이용한 PRPG가 높고 안정된 고장 점검도를 나타내었다.

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The development of the KTX realtime control network$(Tornad^*)$ physical layer based on FPGA (FPGA기반의 KTX용 실시간 제어네트워크$(Tonard^*)$ 물리계층 개발)

  • Hwang, Seung-Kon;Park, Jae-Hyun
    • Proceedings of the KSR Conference
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    • 2007.05a
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    • pp.1735-1740
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    • 2007
  • Communication network in KTX (Korea Train eXpress), the express train system, has to transmit status variables periodically within tens of seconds and real-time control informations which has short reply like status transition or alarm. KTX uses $Tornad^*$ (TOken Ring Network Alsthom Device) network for this purpose. This network can send and receive messages which enable express train applications embedded in intelligence boards to communicate by itself. Layer 1, 2 of $Tornad^*$ is implemented with differential manchester encoding and IEEE 802.4 standard(token bus standard) respectively. To implement layer 1 and 2, we implemented twisted pair modem using FPGA for layer 1 and used MC68824 from Motorola for layer 2. MC68824 bus arbitration and memory controller is implemented using CPLD.

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Implementation and performance evaluation of embedded main-memory storage system for real-time retrieval of multidimensional data (다차원 데이타의 실시간 검색을 위한 내장형 주기억장치 자료 저장시스템의 구성 및 성능평가)

  • Kwon, Oh-Su;Jung, Jae-Bo;Hong, Bong-Kweon
    • Annual Conference of KIPS
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    • 2000.10a
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    • pp.109-112
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    • 2000
  • 이동 단말기 관리, 무인 항공 제어 시스템 둥의 시스템에서는 검색 대상의 정보(위치, 여러 가지 상태등)가 시시각각으로 빠르게 변화하므로 현재의 상태를 정확히 파악하기 위하여 많은 양의 자료 검색, 변경 요청이 빈번히 발생한다. 이와 같은 시스템에서의 상태 정보 검색은 자료의 효용성이 사라지기 전에 이루어져야 하므로 디스크 I/O가 많은 디스크 상주형 데이터베이스로는 한계점을 안고 있다. 또한 빠른 검색을 지원할 수 있는 주기억장치 상주형 데이터베이스로는 다량의 데이터를 저장해야 하는 어려움을 안고 있다. 본 논문에서는 위와 같은 실시간 검색 기능과 대용량 자료 저장의 2가지 요구 사항을 만족시키기 위한 내장형 주기억장치 저장 시스템을 개발하였다.

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A study on the Dislocation-Free Shallow Trench Isolation (STI) Process (Dislocation-Free Shallow Trench Isolation 공정 연구)

  • Yoo, Hae-Young;Kim, Nam-Hoon;Kim, Sang-Yong;Lee, Woo-Sun;Chang, Eui-Goo
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2005.11a
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    • pp.84-85
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    • 2005
  • Dislocations are often found at Shallow Trench Isolation (STI) process after repeated thermal cycles. The residual stress after STI process often leads defect like dislocation by post STI thermo-mechanical stress. Thermo-mechanical stress induced by STI process is difficult to remove perfectly by plastic deformation at previous thermal cycles. Embedded flash memory process is very weak in terms of post STI thermo-mechanical stress, because it requires more oxidation steps than other devices. Therefore, dislocation-free flash process should be optimized.

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Control of Duration Model Parameters in HMM-based Korean Speech Synthesis (HMM 기반의 한국어 음성합성에서 지속시간 모델 파라미터 제어)

  • Kim, Il-Hwan;Bae, Keun-Sung
    • Speech Sciences
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    • v.15 no.4
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    • pp.97-105
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    • 2008
  • Nowadays an HMM-based text-to-speech system (HTS) has been very widely studied because it needs less memory and low computation complexity and is suitable for embedded systems in comparison with a corpus-based unit concatenation text-to-speech one. It also has the advantage that voice characteristics and the speaking rate of the synthetic speech can be converted easily by modifying HMM parameters appropriately. We implemented an HMM-based Korean text-to-speech system using a small size Korean speech DB and proposes a method to increase the naturalness of the synthetic speech by controlling duration model parameters in the HMM-based Korean text-to speech system. We performed a paired comparison test to verify that theses techniques are effective. The test result with the preference scores of 73.8% has shown the improvement of the naturalness of the synthetic speech through controlling the duration model parameters.

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Design of a embedded Linux file system usign MMDB (MMDB로 구현한 내장형 리눅스 파일 시스템 설계)

  • 이동근;김기천
    • Proceedings of the Korean Information Science Society Conference
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    • 2000.04a
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    • pp.130-132
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    • 2000
  • 내장형 파일 시스템을 구현하기 위한 MMDB(Main Memory DB)는 주 기억 장치 상주 메모리 데이터베이스 시스템으로서 이동전화 단말기나 PDA(Personal digital assistants)같이 하드디스크를 가지지 않는 시스템을 대상으로 한다. 하드디스크를 고려하지 않은 점에서 기존의 MMDB와는 다른 메모리 관리 방식이 필요하며, 이를 위한 방안으로 내장형 파일 시스템을 구축하여 효율적인 메모리 관리가 가능하다. 내장형 파일 시스템은 리눅스의 가상 파일 시스템과 유사한 기능을 제공하여 다양한 형태의 파일 시스템을 쉽게 구축하고 사용할 수 있으며, OS가 필요에 따라 파일 시스템의 설정을 변경하여 사용할 수 있다. 또한 OS의 메모리관리자와 파일 시스템의 중복 기능을 제거함으로써 시스템의 성능을 개선시킬수 있고, 데스크 탑 PC와의 데이터 호환성을 향상시킬 수 있다.

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1Kbit single-poly EEPROM IC design (1Kbit single-poly EEPROM IC 설계)

  • Jung, In-Seok;Park, Keun-Hyung;Kim, Kuk-Hwan
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.06a
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    • pp.249-250
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    • 2008
  • In this paper, we propose the single polycrystalline silicon flash EEPROM IC with a new structure which does not need the high voltage switching circuit. The design of high voltage switching circuits which are needed for the data program and erase, has been an obstacle to develop the single-poly EEPROM. Therefore, we has proposed the new cell structure which uses the low voltage switching circuits and has designed the full chip. A new single-poly EEPROM cell is designed and the full chip including the control block, the analog block, row decoder block, and the datapath block is designed. And the each block is verified by using the computer simulation. In addition, the full chip layout is performed.

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A Study on the Improvement of the Method for Implementing Protection Algorithm by using Component Object Model(COM) (컴포넌트 오브젝트 모델을 응용한 계전 알고리즘 구현방법의 개선에 관한 연구)

  • Park, In-Kwon;Yoon, Nam-Seon;An, Bok-Shin
    • Proceedings of the KIEE Conference
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    • 1998.07c
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    • pp.1210-1212
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    • 1998
  • The complexity of newly developed protection algorithm and higher performance requested by the user makes the software embedded in the protective relay much harder to develop and maintain. The versatility of 32bit microprocessor and the availability of cheaper memory semiconductors introduced the fertile developing background for the protective relay developers. The use of component object model(COM) in the software developing process enables the developer to write much complex code in the easy and safe way and to maintain the code easily, too. And the aid of the COM library, the distributed computing environment will be expected to appear by the use of the COM programming model in the protective relay firmware program.

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Concurrent Support Vector Machine Processor (Concurrent Support Vector Machine 프로세서)

  • 위재우;이종호
    • The Transactions of the Korean Institute of Electrical Engineers D
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    • v.53 no.8
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    • pp.578-584
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    • 2004
  • The CSVM(Current Support Vector Machine) that is a digital architecture performing all phases of recognition process including kernel computing, learning, and recall of SVM(Support Vector Machine) on a chip is proposed. Concurrent operation by parallel architecture of elements generates high speed and throughput. The classification problems of bio data having high dimension are solved fast and easily using the CSVM. Quadratic programming in original SVM learning algorithm is not suitable for hardware implementation, due to its complexity and large memory consumption. Hardware-friendly SVM learning algorithms, kernel adatron and kernel perceptron, are embedded on a chip. Experiments on fixed-point algorithm having quantization error are performed and their results are compared with floating-point algorithm. CSVM implemented on FPGA chip generates fast and accurate results on high dimensional cancer data.