• Convergence Security Journal
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• v.6 no.2
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• pp.43-51
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• 2006

The existing electronic transaction protocol uses a cryptography algorithm that is not suitable for mobile environment because of limited memory and process ability. In this paper, we propose an efficient transaction protocol suitable for mobile embedded system. The proposed protocol reduces computation and process time by using ID-based cryptography algorithm and ECC (elliptic curve cryptosystem). It uses vendor authentication only in the first transaction, and from the second transaction, it requires transaction after authentication with session created by applying ECC technique. Therefore, the creation number of authentication for the vendor can be reduced from n to one. And it reduces process time because it provides the same security with 160 bits as with 1024 bits of RSA.

• ETRI Journal
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• v.30 no.4
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• pp.576-586
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• 2008

In most parallel loops of embedded applications, every iteration executes the exact same sequence of instructions while manipulating different data. This fact motivates a new compiler-hardware orchestrated execution framework in which all parallel threads share one fetch unit and one decode unit but have their own execution, memory, and write-back units. This resource sharing enables parallel threads to execute in lockstep with minimal hardware extension and compiler support. Our proposed architecture, called multithreaded lockstep execution processor (MLEP), is a compromise between the single-instruction multiple-data (SIMD) and symmetric multithreading/chip multiprocessor (SMT/CMP) solutions. The proposed approach is more favorable than a typical SIMD execution in terms of degree of parallelism, range of applicability, and code generation, and can save more power and chip area than the SMT/CMP approach without significant performance degradation. For the architecture verification, we extend a commercial 32-bit embedded core AE32000C and synthesize it on Xilinx FPGA. Compared to the original architecture, our approach is 13.5% faster with a 2-way MLEP and 33.7% faster with a 4-way MLEP in EEMBC benchmarks which are automatically parallelized by the Intel compiler.

• IEMEK Journal of Embedded Systems and Applications
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• v.12 no.1
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• pp.1-10
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• 2017

Recently, with the ever-increasing complexity of industrial robot systems, it has been greatly attention to adopt a multi-core based motion controller with high cost-performance ratio. In this paper, we propose a software architecture that aims to utilize the computing power of multi-core processors. The key concept of our architecture is to use shared memory for the interplay between threads running on separate processor cores. And then, we have integrated our proposed architecture with an industrial standard compliant IDE for automatic code generation of motion runtime. For the performance evaluation, we constructed a test-bed consisting of a motion controller with Preempt-RT Linux based dual-core industrial PC and a 3-axis industrial robot platform. The experimental results show that the actuation time difference between axes is 10 ns in average and bounded up to 689 ns under $1000{\mu}s$ control period, which can come up with real-time performance for industrial robot.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.5B
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• pp.526-531
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• 2009

In this paper, we propose new novel technique (ILCT: Instruction-Level Correlation Technique) which can detect tempered instructions by software attacks or hardware attacks before their execution. In conventional works, due to both high complex computation of cipher process and low processing speed of cipher modules, existing secure processor architecture applying cipher technique can cause serious performance degradation. While, the secure processor architecture applying ILCT with FEC does not incur excessive performance decrease by complexity of computation and speed of tampering detection modules. According to experimental results, total memory overhead including parity are increased in average of 26.62%. Also, secure programs incur CPI degradation in average of $1.20%{\sim}1.97%$.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.7 no.5
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• pp.901-906
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• 2006

In this paper, we describe the implementation of the digital photo frame system that displays the images coming through the memory card of a digital camera. Each image can be recorded with voice in this system, and a function of the mp3 player is implemented as well. We use Intel PXA255 to control the system and modify the bootloader and linux kernel. Also we adapt device driver for this system. For the realization of image display, voice recording and mp3 playing in the basis of the linux system, we program some of the Microwindows system configuration files and program applications here. This study will be a good example to access the development of the digital photo frame based on the linux system using less-power and high performed embedded processor.

• The KIPS Transactions:PartA
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• v.9A no.4
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• pp.421-428
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• 2002

In this paper, we have developed an E-book reader for EBKS XML documents on the embedded Linux environment. This reader operated on a Linux target board parses the EBKS XML documents using the Qt SAX interface and displays the parsed pages through the QWS (Qt Windows System) which is a cross-platform windows toolkit. This reader can be easily and rapidly developed on Linux as well as MS windows and requires less memory than DOM interfaces because it parses with SAX interface.

• IEMEK Journal of Embedded Systems and Applications
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• v.14 no.1
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• pp.51-61
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• 2019

There are strict evaluation processes before using new processors to satellites. Engineers evaluate processors from various viewpoints including specification, development environment, and cost. From a viewpoint of computation power, manufacturers provide benchmark results with processors, and engineers decide which processors are adequate to their satellites by comparing the benchmark results with requirements of their satellites. However, the benchmark results depends on a test environment of manufacturers, and it is quite difficult to achieve similar performance in a target environment. Therefore, it is necessary to evaluate the processors in the target environment. This paper compares performance of a processor, AT697F/LEON2, in software testbed (STB) with three development boards of XC2V/LEON3, GR712RC/LEON3, and GR740/LEON4. Seven benchmark functions of Dhrystone, Stanford, Coremark, Whetstone, Flops, NBench, and MiBench are selected. Results are analyzed with hardware and software properties: hardware properties of core architecture, number of cores, cache, and memory; and software properties of build options and compilers. Based on the analysis, this paper describes a guideline for choosing processors for next generation satellites.

• IEMEK Journal of Embedded Systems and Applications
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• v.14 no.5
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• pp.249-258
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• 2019

In the cyber-physical system, big data collected from numerous sensors and IoT devices is transferred to the Cloud for processing and analysis. When transferring data to the Cloud, merging data into one single file is more efficient than using the data in the form of split files. However, current merging and splitting operations are performed at the user-level and require many I / O requests to memory and storage devices, which is very inefficient and time-consuming. To solve this problem, this paper proposes kernel-level partitioning and combining operations. At the kernel level, splitting and merging files can be done with very little overhead by modifying the file system metadata. We have designed the proposed algorithm in detail and implemented it in the Linux Ext4 file system. In our experiments with the real Cloud storage system, our technique has achieved a transfer time of up to only 17% compared to the case of transferring split files. It also confirmed that the time required can be reduced by up to 0.5% compared to the existing user-level method.

• IEMEK Journal of Embedded Systems and Applications
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• v.16 no.4
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• pp.153-161
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• 2021

Real-time access is required to handle continuous and unstructured data and should be flexible in management under dynamic state. Platform can be built to allow data collection, storage, and processing from local-server or multi-server. Although the former centralize method is easy to control, it creates an overload problem because it proceeds all the processing in one unit, and the latter distributed method performs parallel processing, so it is fast to respond and can easily scale system capacity, but the design is complex. This paper provides data collection and processing on one platform to derive significant insights from various data held by an enterprise or agency in the latter manner, which is intuitively available on dashboards and utilizes Spark to improve distributed processing performance. All service utilize dockers to distribute and management. The data used in this study was 100% collected from Kafka, showing that when the file size is 4.4 gigabytes, the data processing speed in spark cluster mode is 2 minute 15 seconds, about 3 minutes 19 seconds faster than the local mode.

• Journal of Korea Multimedia Society
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• v.14 no.1
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• pp.103-111
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• 2011

Legacy Java card which adapts a Java platform loads and executes an application when electronics power is provided. However, recently the most Java cards are embedded into a mobile terminal as USIM cards, therefore the power is continually provided for the smart cards. In this case, operation of a Java card system needs to consider its operating system to be advanced in memory management, object management and transaction mechanism. In this paper, we present a high performance Java Card system which is able to have efficient installation, loading and execution of application by applying a new memory management of the smart card that has safe power system.