• Annual Conference of KIPS
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• 2003.11a
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• pp.467-470
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• 2003

한 개의 자바 프로그램은 다수 개의 클래스 파일로 구성된다. 자바 프로그램이 실행되기 위해서는 클래스 파일이 메모리에 적재되어져야 하는데, 본 논문에서는 개별 클래스들이 어느 정도의 메모리를 사용할지를 정적으로 예측할 수 있게 하는 방법에 대해 알아보았다. 본 논문의 관심은 클래스 영역의 메모리, 즉 정적 메모리에 맞추어져 있으며, 힙 영역의 메모리 등 동적 메모리에 대한 예측은 향후 연구로 남겨 두었다. 클래스를 이루는 필드와 메소드 등의 값들이 메모리 사용량에 미치는 영향을 수식으로 유도하였으며, 이 수식의 유효성을 실제 실험을 통해 확인하였다.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.120-123
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• 2000

In this paper, A target architecture and interface synthesizer are proposed for processor-embedded codesign. The target architecture has the form of ARM processor based on AMBA. The interface synthesizer automatically generates an interface circuit for the communication between HW and SW. A memory map is used as the communication channel and an interrupt-based interface is applied for synchronized communication between HW and SW modules. In order to verify the function and performance of proposed target architecture and the interface synthesizer, practical test example is applied. Experimental results show the proposed interface synthesizer functioned correctly in the HW/SW codesign environment.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.1137-1140
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• 1999

In this thesis, we research about Communication System Construction and Test-Bed Realization Method and Software’s Design with written program into Embedded Micro Controller’s restricted memory region using a DSP Chip to deal with mainly high speed communication. Tools used for modern communication network control use TI or AMD general chip class, but nevertheless responsibility for the point at issue, Analog Device is architecture design model moderated for small communication system. In this thesis, we present extended model, and realize basic case.

• 한국컴퓨터산업교육학회:학술대회논문집
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• 2003.11a
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• pp.111-118
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• 2003

Java Card API written to optimize Execute Environment in embedded device of small memory such as smart card. Java Card API intended to provide many advance when develope smart card based program. this paper purpose to implement RSA Algorithm of public key Algorithms with Java Card API.

• Proceedings of the Korean Vacuum Society Conference
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• 2008.02a
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• pp.126-126
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• 2008

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.6
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• pp.310-316
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• 2001

본 논문에서는 10N March 테스트 알고리즘에 기반한 내장된 이중 포트 메모리를 위한 효율적인 테스트 알고리즘을 제안하였다. 제안된 알고리즘은 각각의 포트에 대해 독립적으로 테스트 알고리즘을 적용함으로써 각각의 포트에 대해서 단일 포트 메모리 테스트 알고리즘을 적용하는 방법에 비해 시간 복잡도를 20N에서 8.5N으로 시간 복잡도를 줄였다. 그리고 제안된 알고리즘은 주소 디코더 고장, 고착 고장, 천이 고장, 반전 결합 고장, 동행 결합 고장을 모두 검출할 수 있다.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.09a
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• pp.3-17
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• 2003

.Package Trend -> Memory : Lighter, Thinner, Smaller & High Density => SiP, 3D Stack -> MPU : High Pin Counts & Multi-functional => FCBGA .Interposer Trend -> Via - Unfilled Via => Filled Via - Staggered Via => Stacked Via -> Emergence of All-layer Build-up Processes -> Interposer Material Requirement => Low CTE, Low $D_{k}$, Low $D_{f}$, Halogen-free .New Technology Concept -> Embedded Passives, Imprint, MLTS, BBUL etc.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2003.11a
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• pp.259-264
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• 2003

In this paper, web based monitoring systems are implemented using embedded Linux. The external equipment is controlled via HTTP protocol and web browser program. HTTP protocol is ported into Linux. A micro web server program and external equipment control program are installed on-board memory using CGI to be accessed by web browser. Experimental result of the proposed web based monitoring systems can be used in automation systems and remote distributed control via internet using web browser.

• Annual Conference of KIPS
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• 2002.04b
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• pp.1631-1634
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• 2002

본 논문에서는 PC상에서 내장 메모리를 테스트 할 수 있는 테스트 시스템을 구현하였다. 테스트상으로는 Synchronous DRAM을 사용하였고 내장 자체 테스트 회로에 10N March C 알고리즘을 적용, DSRAM, SRAM을 제어하는 테스트 시스템 제어기를 설계하였다. 본 테스트 시스템은 메모리 테스트 검증을 고가의 테스트 장비 없이 용이하게 하도록 설계되었다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.101-109
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• 2009

Generally, depth cache and pixel cache of 3D graphics are designed by using write-back scheme for efficient use of memory bandwidth. Also, there are write after read operations of same address or only write operations are occurred frequently in 3D graphics cache. If a cache miss is detected, an access to the external memory for write back operation and another access to the memory for handling the cache miss are operated simultaneously. So on frequent cache miss situations, as the memory access bandwidth limited, the access time of the external memory will be increased due to memory bottleneck problem. As a result, the total performance of the processor or the IP will be decreased, also the problem will increase peak power consumption. So in this paper, we proposed a novel early write back cache architecture so as to solve the problems issued above. The proposed architecture controls the point when to access the external memory as to copy the valid data block. And this architecture can improve the cache performance with same hit ratio and same capacity cache. As a result, the proposed architecture can solve the memory bottleneck problem by preventing intensive memory accesses. We have evaluated the new proposed architecture on 3D graphics z cache and pixel cache on a SoC environment where ARM11, 3D graphic accelerator and various IPs are embedded. The simulation results indicated that there were maximum 75% of performance increase when using various simulation vectors.