• The Journal of Information Technology
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• v.3 no.3
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• pp.57-65
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• 2000

We have proposed BIST method and circuit for embedded 16M SDRAM with logic. It can test the AC parameter of embedded 16M SDRAM using the BIST circuit capable of detecting the address of a fail cell of a 16M SDRAM installed in an Merged Memory with Logic(MML) generating the information of repair for redundancy circuit. The function and AC parameter of the embedded memory can also be tested using the proposed BIST method. The total gate of the BIST circuit is approximately 4,500 in the case of synthesizing by $0.25\mu\textrm{m}$ cell library. and verify the result of Verilog simulation. The test time of each one AC parameter is about 200ms using 2Y-March 14N algorithm.

• Journal of Korea Multimedia Society
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• v.20 no.5
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• pp.769-781
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• 2017

Deep learning networks like Convolutional Neural Networks (CNNs) show successful performances in many computer vision applications such as image classification, object detection, and so on. For implementation of deep learning networks in embedded system with limited processing power and memory, deep learning network may need to be simplified. However, simplified deep learning network cannot learn every possible scene. One realistic strategy for embedded deep learning network is to construct a simplified deep learning network model optimized for the scene images of the installation place. Then, automatic training will be necessitated for commercialization. In this paper, as an intermediate step toward automatic training under fisheye camera environments, we study more precise human localization in fisheye images, and propose an accurate human localization method, Automatic Ground-Truth Labelling Method (AGTLM). AGTLM first localizes candidate human object bounding boxes by utilizing GoogLeNet-LSTM approach, and after reassurance process by GoogLeNet-based CNN network, finally refines them more correctly and precisely(tightly) by applying saliency object detection technique. The performance improvement of the proposed human localization method, AGTLM with respect to accuracy and tightness is shown through several experiments.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.42 no.4 s.304
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• pp.11-16
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• 2005

Class area is a portion of memory where the constants, fields, and codes of the classes loaded into the Java virtual machine are kept. Knowing the size of the class area is very important especially for embedded Java system with limited memory resources. This paper induces a formula which makes it possible estimate the size of the area. The formula needs some constant values specific to target JVM implementation. We also show that these values can be found using some simple probe classes. An experimental result is included in this paper to confirm the correctness of our approach.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.6
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• pp.1301-1306
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• 2011

RTOS in the embedded system is a powerful tool for the design of multi-tasking. However, previous RTOS has large proportion in the MCU with limited memory. So it is difficult to apply RTOS. In this paper, I removed less frequently used features from the traditional RTOS, and designed lightweight RTOS that schedules and manages the resources with minimal code. I used techniques to obtain user memory using sharing stack, and to reduce the overhead at context. Considering ratio of kernel and applications, the RTOS designed in this paper is available on the MCU with more than 4KB of program memory.

• IEMEK Journal of Embedded Systems and Applications
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• v.12 no.3
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• pp.149-157
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• 2017

In this paper, we propose BCMR (Block Classification with Monitor and Restriction) to ensure the isolation and to reduce the interference of blocks between a garbage collection and a wear leveling. The proposed BCMR monitors an endurance variation of blocks during the garbage collection and detects hot blocks by making a restriction condition based on this information. The proposal induces a block classification by its update frequency for the garbage collection and the wear leveling, so we will get a prolonged lifetime of NAND flash memory systems. In a performance evaluation, BCMR prolonged the lifetime of NAND flash memory systems by 3.95%, on average and reduced a standard deviation per block by 7.4%, on average.

• IEMEK Journal of Embedded Systems and Applications
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• v.13 no.5
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• pp.269-277
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• 2018

NAND flash memory has widely been used because of non-volatility, low power consumption and fast access time. However, it suffers from inability to provide update-in-place and the erase cycle is limited. The unit of read/write operation is a page and the unit of erase operation is a block. Moreover erase operation is slower than other operations. We proposed the Adaptive Garbage Collection (called "AGC") policy which focuses on not only reducing garbage collection process time for real-time guarantee but also wear-leveling for a flash memory lifetime. The AGC performs better than Cost-benefit policy and Greedy policy. But the AGC does not consider the operation characteristics. So we proposed the Advanced Adaptive Garbage Collection (called "A-AGC") policy which considers the page write operation count and block erase operation count. The A-AGC reduces the write operations by considering the data update frequency and update data size. Also, it reduces the erase operations by considering the file fragmentation. We implemented the A-AGC policy and measured the performance compared with the AGC policy. Simulation results show that the A-AGC policy performs better than AGC, specially for append operation.

• IEMEK Journal of Embedded Systems and Applications
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• v.18 no.1
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• pp.31-40
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• 2023

Recent advances in flash technologies, such as 3D processing and multileveling schemes, have successfully increased the flash capacity. Unfortunately, these technology advances significantly degrade flash's reliability due to a smaller cell geometry and a finer-grained cell state control. In this paper, we propose an asymmetric BER-aware reliability optimization technique (aBARO), new flash optimization that improves the flash reliability. To this end, we first reveal that bit errors of 3D NAND flash memory are highly skewed among flash cell states. The proposed aBARO exploits the unique per-state error model in flash cell states by selecting the most error-prone flash states and by forming narrow threshold voltage distributions (for the selected states only). Furthermore, aBARO is applied only when the program time (tPROG) gets shorter when a flash cell becomes aging, thereby keeping the program latency of storage systems unchanged. Our experimental results with real 3D MLC and TLC flash devices show that aBARO can effectively improve flash reliability by mitigating a significant number of bit errors. In addition, aBARO can also reduce the read latency by 40%, on average, by suppressing the read retries.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.102-107
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• 2007

This paper proposes a H.264/AVC entropy decoder without embedded processor nor memory fabrication process. Many researches on H.264/AVC entropy decoders require ROM or RAM fabrication process, which is difficult to be implemented in general digital logic fabrication process. Furthermore, many researches require embedded processors for bitstream manipulation, which increases area and power consumption. This papers proposes hardwired H.264/AVC entropy decoder without embedded processor, which improves data processing speed and reduces power consumption. Furthermore, its CAVLC decoder optimizes lookup table and internal buffer without embedded memory, which reduces hardware size and can be implemented in general digital logic fabrication process without ROM or RAM fabrication process. Designed entropy decoder was embedded in H.264/AVC video decoder, and it was verified to operate correctly in the system. Synthesized in TSMC 90nm fabrication process, its maximum operation frequency is 125MHz. It supports QCIF, CIF, and QVGA image format. Under slight modification of nC register and other blocks, it also support VGA image format.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.3 s.309
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• pp.20-29
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• 2006

The Java language has been established as one of the most widely used language due to its object-oriented programming, safety and flexibility and the garbage collection of the virtual machine has relieved programmers of many difficulties related to the memory management. In the embedded environment, Java is also prevalent, the virtual machine and garbage collector that takes into account the embedded environment is required. In this paper we manage the heap memory area by dividing into young generation and old generation, and we propose a garbage collector in which appropriate techniques are applied to each generation to utilize the different characteristics of each generation. Also, we propose the write barrier technique and double filtering technique for efficient garbage recognition, and double check method for determining and reclaiming the garbage with cyclic structure. The proposed method satisfies the embedded environment's requirements of fast object allocation, real time property, recollection of all the garbage, elimination of fragmentations and high locality.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.311-311
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• 2013

The resistance switching memory devices have several advantages to take breakthrough for the limitation of operation speed, retention, and device scale. Especially, the metal-oxide materials such as ZnO are able to fabricate on the flexible and visible transparent plastic substrate. Also, the quantum dots (QDs) embedded in dielectric layer could be improve the ratio between the low and the high resistance becauseof their Coulomb blockade, carrier trap and induced filament path formation. In this study, we irradiated 0.2-MeV-electron beam on the ZnO/QDs/ZnO structure to control the defect and oxygen vacancy of ZnO layer. The metal-oxide QDs embedded in ZnO layer on Pt/glass substrate were fabricated for a memory device and evaluated electrical properties after 0.2-MeV-electron beam irradiations. To formation bottom electrode, the Pt layer (200 nm) was deposited on the glass substrate by direct current sputter. The ZnO layer (100 nm) was deposited by ultra-high vacuum radio frequency sputter at base pressure $1{\times}10^{-10}$ Torr. And then, the metal-oxide QDs on the ZnO layer were created by thermal annealing. Finally, the ZnO layer (100 nm) also was deposited by ultra-high vacuum sputter. Before the formation top electrode, 0.2 MeV liner accelerated electron beams with flux of $1{\times}10^{13}$ and $10^{14}$ electrons/$cm^2$ were irradiated. We will discuss the electrical properties and the physical relationships among the irradiation condition, the dislocation density and mechanism of resistive switching in the hybrid memory device.