• Proceedings of the IEEK Conference
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• 2002.06a
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• pp.379-382
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• 2002

This paper describes an experiment on the embedded network agent. The embedded network agent is the device that will enable other devices to communicate over the Internet. Many devices have no way to communicate with other devices over the Internet The embedded network agent extends the stand-alone devices that have no TCP/IP protocol suite to the Internet, the global networks, without any hardware and software. To support the better efficiency, this parer proffers new TCP state diagram of the embedded network agent. This TCP state on the embedded network agent considers the status of the common devices behind the embedded network agent. Because of this consideration, the embedded network agent tenders an improved result to user.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.608-611
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• 2003

A large part of the embedded system, compared with the PC, have low performance CPU and small memory. So the embedded operating system fits the condition of that hardware system. A Single Address Space (SAS) OS has the operating system and all applications in the single address space. The SAS architecture enhances sharing and co-operation, because addresses have a unique interpretation. Thus, pointer-based date structures can be directly communicated and shared between programs at any time, and can be stored directly on storage. The key point of the SAS OS on the embedded system is the low overhead inter-action between programs in process and usage. So SAS OS can be ported on the low performance CPU. In this paper, we design the SAS OS (named emNOS, Embedded Network Operating System) on the ARMTTDMI processor. Finally we show the benefits of the SAS OS on the embedded system.

• The KIPS Transactions:PartD
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• v.18D no.1
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• pp.45-56
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• 2011

The importance of low-power embedded system is being increased. The studies on low-power system have been performed in issues of hardware architecture and operating system. However because the behaviors of software control the working of hardware devices, the power analysis of software is one of critical issues in energy-efficient embedded system development. This paper proposes a technique to extract tasks from software design models with considering power consumption. We first define the criteria for task extraction, and then propose the way to separate out the task from UML 2.0 design models. Our technique can provide the chance to reduce the power consumption as well as to fulfill the performance requirement in the early phase of software development.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.05a
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• pp.888-889
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• 2015

This paper presents a method of constructing the system-on-chip(SoC) based on embedded systems. The proposed method is more compact and effectiveness than former methods. The requirements generation start high level performance simulation and then passes to an executable specification suitable for implementation using a hardware/software co-design tool. The reuse of pre-exiting components is supported, as well as synthesis of the system interface, but only after much work is done to program the hardware/software co-design tool. The actual design flow described allows feedback among all design levels, e.g. from implementation up to requirements, throughout the process. In the future, it is necessary to development the advanced method of constructing system-on-chip based on embedded systems.

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.2
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• pp.96-102
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• 2014

The embedded processor market has grown rapidly and consistently with the appearance of mobile devices. In an embedded system, the power consumption and execution time are important factors affecting the performance. The system performance is determined by both hardware and software. Although the hardware architecture is high-end, the software runs slowly due to the low quality of codes. This study compared the performance of two major compilers, LLVM and GCC on a32-bit EISC embedded processor. The dynamic instructions and static code sizes were evaluated from these compilers with the EEMBC benchmarks.LLVM generally performed better in the ALU intensive benchmarks, whereas GCC produced a better register allocation and jump optimization. The dynamic instruction count and static code of GCCwere on average 8% and 7% lower than those of LLVM, respectively.

• Journal of Broadcast Engineering
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• v.24 no.6
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• pp.1064-1071
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• 2019

Multiview stereo matching algorithm is used to reconstruct 3D shape from a set of 2D images. Conventional multiview stereo algorithms have been implemented on high-performance hardware due to the heavy complexity that contains a large number of calculations in each step. However, as the performance of mobile graphics processors has recently increased rapidly, complex computer vision algorithms can now be implemented on mobile devices like a smartphone and an embedded board. In this paper we parallelize an multiview stereo algorithm using OpenCL on mobile GPU and provide various optimization techniques on the embedded hardware with limited resource.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.40 no.4
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• pp.214-221
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• 2003

This paper shows an implementation of video codec (coder/decoder) on an embedded system. The video codec supports both H.261 and H.263 standards. For efficient real-time processing, the video codec is partitioned into a software module and a hardware module. Both modules are codesigned on an embedded system. The software module is processed on a real-time operating system and a RISC processor. It cooperates with the hardware module to compress and decompress images in real time. AMBA (Advanced Microcontroller Bus Architecture) AHB (Advanced High-performance Bus) is used as the system bus. The hardware module works both as AHB masters and as AHB slaves. The encoder part of the hardware module operates in a pipelines mode to compress images in real time. The video codec compresses 15 CIF frames and simultaneously decompresses 15 CIF frames in a second according to H.261 or H.263 standard at 33 MHz frequency.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.3
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• pp.664-668
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• 2010

This paper presents a System-On-a-chip (SoC) for embedded image processing and pattern recognition applications that need Gaussian Pyramid structure. The system is fully implemented into Field-Programmable Gate Array (FPGA) based on the prototyping platform. The SoC consists of embedded processor core and a hardware accelerator for Gaussian Pyramid construction. The performance of the implementation is benchmarked against software implementations on different platforms.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.10
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• pp.2059-2063
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• 2009

This paper presents a programmable System-On-a-chip (SoC) for various embedded smart applications that need Neural Network computations. The system is fully implemented into a prototyping platform based on Field Programmable Gate Array (FPGA). The SoC consists of an embedded processor core and a reconfigurable hardware accelerator for neural computations. The performance of the SoC is evaluated using a real image processing application, an optical character recognition (OCR) system.

• Journal of KIISE:Computing Practices and Letters
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• v.6 no.2
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• pp.173-186
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• 2000

Real-time embedded systems should accommodate many kinds of hardware platforms and resource management policies that vary depending on their operating environments and purposes. It is not an easy job to adapt a multitasking kernel to new system services and hardware platforms, as the kernel must strictly satisfy constraints on its size and performance. This paper describes the design and implementation of an object-oriented multitasking framework that can be reused for implementing microprocessor-based real-time embedded multitasking kernels, In this kernel framework, those parts that can vary depending on hardware platforms and system resource management policies are separated into the hot spots and encapsulated by abstract classes. Our framework thus can be effectively used to implement microprocessor-based real-time embedded kernels that demand high portability and adaptability.