• KIISE Transactions on Computing Practices
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• v.21 no.10
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• pp.639-644
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• 2015

The capacity of flash-based storage such as Solid State Drive(SSD) and embedded Multi Media Card(eMMC) is ever-increasing because of the needs from the end-users. However, if a flash-based storage crashes, such as during power failure, the flash translation layer(FTL) is responsible for the crash recovery based on the entire flash memory. The recovery time increases as the capacity of the flash-based storages increases. We propose O1FTL with O(1) crash recovery time that is independent of the flash capacity. O1FTL adopts the working area technique suggested for the flash file system and evaluates the design on a real hardware platform. The results show that O1FTL achieves a crash recovery time that is independent of the capacity and the overhead, in terms of I/O performance, and achieves a low P/E cycle.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.7
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• pp.1520-1525
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• 2009

In this paper, we study and simulate the suggested position control system using GPS and USN to replace the existing control system of a crane. For the correct approach, the position control system of a crane is divided into the control system of the ground station and the mobile station The hardware is comprised of GPS receiving module to receive the position control data of a crane from GPS satellites, bluetooth communication module for the data communication between the ground station and the mobile station, supersonic sensor module for a precise position control of a crane, motor to replace a crane roller, embedded MCU(ATmega128L) and so on. In here, an embedded MCU controls GPS receiving module, bluetooth communication module and supersonic sensor module. The Software is comprised of three programs. Three programs are the program to filter GGA output part in a receiving data of GPS receiving module, the driving program for supersonic sensor module, the digital map program to monitor a crane location. From the simulation results, it is demonstrated that the proposed system has the capability of crane position control with 1cm precision.

• KIISE Transactions on Computing Practices
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• v.21 no.9
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• pp.604-609
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• 2015

The use of Operating System(OS) virtualization is increasing as it provides many useful features such as efficient use of hardware(HW), easy system migration, and isolation between virtual spaces which prevents errors effecting each other. Recent development in HW has made it possible to use OS virtualization in embedded systems. However, implementing OS virtualization means that a multiple number of schedulers are layered in a system, rendering it difficult to analyze the schedulability of the system and errors are easily produced. Errors in safety critical embedded systems can cause serious damage to life and property; thus, the hierarchical schedulability must be verified. In this paper, we propose a framework which supports formal modeling and verification of hierarchical scheduling systems with UPPAAL.

• IEMEK Journal of Embedded Systems and Applications
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• v.16 no.6
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• pp.267-276
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• 2021

The automotive industry and academic research have been continuously conducting research on standardization such as AUTOSAR (AUTomotive Open System ARchitecture) and ISO26262 to solve problems such as safety and efficiency caused by the complexity of electric/electronic architecture of automotive. AUTOSAR is an automotive standard software platform that has a layered structure independent of MCU (Micro Controller Unit) hardware, and improves product reliability through software modularity and reusability. And, ISO26262, an international standard for automotive functional safety and suggests a method to minimize errors in automotive ECU (Electronic Control Unit)s by defining the development process and results for the entire life cycle of automotive electrical/electronic systems. These design methods are variously applied in representative automotive safety-critical systems. However, since the functional and safety requirements are different according to the characteristics of the safety-critical system, it is essential to research the AUTOSAR functional safety design method specialized for each application domain. In this paper, a software functional safety mechanism design method using AUTOSAR is proposed, and a new failure management framework is proposed to ensure the high reliability of the product. The AUTOSAR functional safety mechanism consists of memory partitioning protection, timing monitoring protection, and end-to-end protection. The fault management framework is composed of several safety SWCs to maintain the minimum function and performance even if a fault occurs during the operation of a safety-critical system. Finally, the proposed method is applied to the Shift-by-Wire system design to prove the validity of the proposed method.

• Convergence Security Journal
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• v.21 no.2
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• pp.29-35
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• 2021

UART (Universal asynchronous receiver/transmitter) is a hardware device that converts data into serial format and transmits it, and is widely used for system diagnosis and debugging in most embedded systems. Hackers can access system memory or firmware by using the functions of UART, and can take over the system by acquiring administrator rights of the system. In this paper, we studied secure UART to protect against hacker attacks through UART. In the proposed scheme, only authorized users using the promised UART communication protocol are allowed to access UART and unauthorized access is not allowed. In addition, data is encrypted and transmitted to prevent protocol analysis through sniffing. The proposed UART technique was implemented in an embedded Linux system and performance evaluation was performed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.11
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• pp.1377-1383
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• 2019

Histogram equalization is the most frequently used algorithm for image enhancement. Its hardware implementation significantly outperforms in time its software version. The overall performance of FPGA-based implementation of histogram equalization can be improved by applying pipelining in the design and by exploiting the multipliers and a lot of SRAM blocks which are embedded in recent FPGAs. This work proposes how to implement a fast histogram equalization circuit for 8-bit gray level images. The proposed design contains a FIFO to perform equalization on an image while the histogram for next image is being calculated. Because of some overlap in time for histogram equalization, embedded multipliers and pipelined design, the proposed design can perform histogram equalization on a pixel nearly at a clock. And its dual parallel version outperforms in time almost two times over the original one.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.6
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• pp.850-858
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• 2022

To deploy Gate Recurrent Units (GRU) on resource-constrained embedded devices, this paper presents a reconfigurable FPGA-based GRU accelerator that enables structured compression. Firstly, a dense GRU model is significantly reduced in size by hybrid quantization and structured top-k pruning. Secondly, the energy consumption on external memory access is greatly reduced by the proposed reuse computing pattern. Finally, the accelerator can handle a structured sparse model that benefits from the algorithm-hardware co-design workflows. Moreover, inference tasks can be flexibly performed using all functional dimensions, sequence length, and number of layers. Implemented on the Intel DE1-SoC FPGA, the proposed accelerator achieves 45.01 GOPs in a structured sparse GRU network without batching. Compared to the implementation of CPU and GPU, low-cost FPGA accelerator achieves 57 and 30x improvements in latency, 300 and 23.44x improvements in energy efficiency, respectively. Thus, the proposed accelerator is utilized as an early study of real-time embedded applications, demonstrating the potential for further development in the future.

• IEMEK Journal of Embedded Systems and Applications
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• v.17 no.1
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• pp.33-40
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• 2022

With the recent increase in the development of military drones, they are adopted and used as the combat system of battalion level or higher. However, it is difficult to use drones that can be used in battles below the platoon level due to the current conditions for the formation of units in the Korean military. In this paper, therefore, we developed a program drones equipped with a thermal imaging camera and LiDAR sensor for reconnaissance and exploration that can be applied in battles below the platoon level. Using these drones, we studied the possibility and feasibility of drones for small-scale combats that can find hidden enemies, search for an appropriate detour through image processing and conduct reconnaissance and search for battlefields, hiding and cover-up through image processing. In addition to the purpose of using the proposed drone to search for an enemies lying in ambush in the battlefield, it can be used as a function to check the optimal movement path when a combat unit is moving, or as a function to check the optimal place for cover-up or hiding. In particular, it is possible to check another route other than the route recommended by the program because the features of the terrain can be checked from various viewpoints through 3D modeling. We verified the possiblity of flying by designing and assembling in a form of adding LiDAR and thermal imaging camera module to a drone assembled based on racing drone parts, which are open source hardware, and developed autonomous flight and search functions which can be used even by non-professional drone operators based on open source software, and then installed them to verify their feasibility.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.45 no.6
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• pp.117-122
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• 2008

Although the pulse diagnosis is the one of the most important diagnostic process to traditional medical doctors, there is no proper communication tool between experts and trainees. In this paper, we have developed a indentation training system which consists of a hardware measuring indent pressure on artificial arm quantitatively and a software providing a indentation training program. The hardware for measurement of indent pressure profile includes 3 load cells embedded in the artificial arm, signal amplification part and digitization part, NI-USB 6009 with 200Hz sampling rate. For setting up a relationship table between weights and output voltages, 8 standard weights were used. To evaluate this hardware, 3 oriental medical specialists were involved and their indent pressure profile were recorded three times respectively. From these, it was found that pulse diagnosis process could be divided into 3 periods and the maximum load were $500g{\cdot}f$ approximately while doctors perform a pulse diagnosis. The indentation training program was implemented with LabView and designed to monitor the differences between the pressure profile of a expert and that of a trainee so to offer some visual feedback to the trainee. Also, this program could provide the trends of training performances. With this developed system, the education of pulse diagnosis is expected to be more quantitative and effective.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.9_10
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• pp.485-496
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• 2008

As the complexity of SoC (System-on-Chip) design increases dramatically. traditional system performance analysis and verification methods based on RTL (Register Transfer Level) are no more valid for increasing time-to-market pressure. Therefore a new design methodology is desperately required for system verification in early design stages. and hardware software (HW-SW) cosimulation at TLM (Transaction Level Modeling) level has been researched widely for solving this problem. However, most of HW-SW cosimulators support few restricted ion levels only, which makes it difficult to integrate HW-SW cosimulators with different ion levels. To overcome this difficulty, this paper proposes a multipurpose framework for HW SW cosimulation to provide systematic SoC design flow starting from software application design. It supports various design techniques flexibly for each design step, and various HW-SW cosimulators. Since a platform design is possible independently of ion levels and description languages, it allows us to generate simulation models with various ion levels. We verified the proposed framework to model a commercial SoC platform based on an ARM9 processor. It was also proved that this framework could be used for the performance optimization of an MJPEG example up to 44% successfully.