• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2021.10a
• /
• pp.643-645
• /
• 2021

Minecraft Pi edition is a distinct version of Minecraft developed for Raspberry Pi and was mostly used as an educational instrument for upcoming programmers. In this paper, the basic method to control GPIO pin of Raspberry Pi 4 board using python 3 and Minecraft Pi software was implemented. The implemented scheme can be easily applicable to the area of educational platform and metaverse application if a plenty of python libraries embedded in raspberry pi and excellent gaming capability of Minecraft Pi software are efficiently merged to meet application-specific hardware and software requirements.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.4
• /
• pp.43-54
• /
• 2007

This paper presents design and verification of a face detection hardware for real time application. Face detection algorithm detects rough face position based on already acquired feature parameter data. The hardware is composed of five main modules: Integral Image Calculator, Feature Coordinate Calculator, Feature Difference Calculator, Cascade Calculator, and Window Detection. It also includes on-chip Integral Image memory and Feature Parameter memory. The face detection hardware was verified by using S3C2440A CPU of Samsung Electronics, Virtex4LX100 FPGA of Xilinx, and a CCD Camera module. Our design uses 3,251 LUTs of Xilinx FPGA and takes about 1.96${\sim}$0.13 sec for face detection depending on sliding-window step size, when synthesized for Virtex4LX100 FPGA. When synthesized on Magnachip 0.25um ASIC library, it uses about 410,000 gates (Combinational area about 345,000 gates, Noncombinational area about 65,000 gates) and takes less than 0.5 sec for face realtime detection. This size and performance shows that it is adequate to use for embedded system applications. It has been fabricated as a real chip as a part of XF1201 chip and proven to work.

• Journal of the Korean Society for Aeronautical & Space Sciences
• /
• v.38 no.12
• /
• pp.1217-1222
• /
• 2010

This paper describes the Model-Based Development(MBD) process behind the flight control software of a close-range unmanned aerial vehicle(KUS-9). An integrated development environment was created using a commercial tool(MATLAB $Simulink^{(R)}$), which was utilized to design models for linear/nonlinear simulation, flight control law, operational logic and HILS(Hardware In the Loop Simulation) system. Software requirements were validated through flight simulations and peer reviews during the design process, whereas the models were verified through the application of a DO-178B verification tool. The integrity of automatically generated C code was verified by using a separate S/W testing tool. The finished software product was embedded on two different types of hardware and real-time operating system(uC/OS-II, VxWorks) to perform HILS and flight tests. The key findings of this study are that MBD Technology enables the development of a reusable and an extensible software product and auto-code generation technology allows the production of a highly reliable flight control software under a compressed time schedule.

• Proceedings of the Korean Institute of Intelligent Systems Conference
• /
• 1993.06a
• /
• pp.975-976
• /
• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}

• Journal of Korea Multimedia Society
• /
• v.12 no.3
• /
• pp.335-344
• /
• 2009

Embedded systems and web browsers have started to provide two-dimensional vector graphics features, to finally support scalability of graphics outputs, while traditional graphics systems have focused on the raster and bitmap operations. Nowadays, SVG and Flash are actively used while OpenVG from Khronos group plays the role of a de facto low-level API standard to support them. In this paper, we represent the design and implementation process and the final results of an OpenVG implementation, AlexVG. From its design stage, our implementation aims at the cooperation with SVG-Tiny, another de facto standard for embedded systems. Currently, our overall system provides not only the OpenVG core features but also variety of OpenVG application programs and SVG-Tiny media file playing capabilities. For the conformance with the standard specifications, our system completely passed the whole OpenVG conformance test suites and the graphics output portions of the SVG-Tiny conformance test suites. From the performance point of view, we focused on the efficiency and effectiveness especially on the mobile phones and embedded devices with limited resources. As the result, it showed impressive benchmarks on the small-scale CPU's such as ARM's, even without neither any other libraries nor acceleration hardware.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.13 no.3
• /
• pp.623-628
• /
• 2009

The emergence of compact and low-power wireless communication sensors and actuators in the technology supporting the ongoing miniaturization of processing and storage allows for entirely the new kinds of embedded systems. These systems are distributed and deployed in environments where they may have been designed into a particular control method, and are often very dynamic. Collection of devices can communicate to achieve a higher level of coordinated behavior. Wireless sensor nodes deposited in various places provide light, temperature, and activity measurements. Wireless sensor nodes attached to circuits or appliances sense the current or control the usage. Together they form a dynamic and multi-hop routing network connecting each node to more powerful networks and processing resources. Wireless sensor networks are a specific-application and therefore they have to involve both software and hardware. They also use protocols that relate to both applications and the wireless network. Wireless sensor networks are consumer devices supporting multimedia applications such as personal digital assistants, network computers, and mobile communication devices. Wireless sensor networks are becoming an important part of industrial and military applications. The characteristics of modem embedded systems are the capable of communicating adapting the different operating environments. In this paper, We designed and implemented sensor network system which shows through host PC sensing temperature and humidity data transmitted for wireless sensor nodes composed wireless temperature and humidity sensor and designs sensor nodes using embedded system with the intention of studying USN.

• Journal of Internet Computing and Services
• /
• v.14 no.1
• /
• pp.31-39
• /
• 2013

Generally, there can be a interface discrepancy between the legacy hardware and the new software in combining new software component with reused hardware components in the embedded system. This kind of the interface discrepancy may cause various types of faults and also result in declining interface fault tolerance. In this paper we propose a method to improve interface fault tolerance. First of all, the new interface discrepancy fault type which has not been dealt with before is to be defined and next the testing method for generating test paths is proposed by considering the new defined interface discrepancy fault type in this paper. Several tests show that the proposed method detects more fatal faults about 7.9% in comparison with the existing testing method for commercial broadcasting receiver. Since the proposed method can provide software developers with test paths to be available earlier on the software development cycle, in addition, software developers can regard on interface discrepancy fault in advance. Consequently, more efficient test planning can be established to improve the interface fault tolerance.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.48 no.3
• /
• pp.62-70
• /
• 2011

Nowadays image sensor is an essential component in many multimedia devices, and it is covered by a color filter array to filter out specific color components at each pixel. We need a certain algorithm to combine those color components reconstructed a full color image from incomplete color samples output from an image sensor, which is called a demosaicking process. Most existing demosaicking algorithms are developed for ideal image sensors, but they do not work well for the practical cases because of dissimilar characteristics of each sensor. In this paper, we propose a new demosaicking algorithm in which the color filter characteristics are fully utilized to generate a good image. To demonstrate significance of our algorithm, we used a commerically available sensor, CBN385B, which is a sort of Honeycomb-style CFA(Color Filter Array) CCD image sensor. As a performance metric of the algorithm, PSNR(Peak Signal to Noise Ratio) and RGB distribution of the output image are used. We first implemented our algorithm in C-language for simulation on various input images. As a result, we could obtain much enhanced images whose PSNR was improved by 4~8 dB compared to the commonly idealized approaches, and we also could remove the inclined red property which was an unique characteristics of the image sensor(CBN385B).Then we implemented it in hardware to overcome its problem of computational complexity which made it operate slow in software. The hardware was verified on Spartan-3E FPGA(Field Programable Gate Array) to give almost the same performance as software, but in much faster execution time. The total logic gate count is 45K, and it handles 25 image frmaes per second.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.12
• /
• pp.79-90
• /
• 2005

In this paper, we propose a new clustered reconfigurable interconnect network (CRIN) BIST to improve the embedding probabilities of random-pattern-resistant-patterns. The proposed method uses a scan-cell reordering technique based on the signal probabilities of given test cubes and specific hardware blocks that increases the embedding probabilities of care bit clustered scan chain test cubes. We have developed a simulated annealing based algorithm that maximizes the embedding probabilities of scan chain test cubes to reorder scan cells, and an iterative algorithm for synthesizing the CRIN hardware. Experimental results demonstrate that the proposed CRIN BIST technique achieves complete fault coverage with lower storage requirement and shorter testing time in comparison with the conventional methods.

• Journal of the Korea Computer Graphics Society
• /
• v.17 no.2
• /
• pp.37-43
• /
• 2011

OpenVG and SVG Tiny are the most widely used 2D vector graphics technologies for outputs in the various embedded environments including smart phones. Especially, to show high refresh rates on the high resolution screens, it is necessary to effectively accelerate them. Until now, OpenVG and SVG Tiny are available as hardware implementations such as the fully-dedicated graphics chips or full software implementations. Currently available vector graphics silicon chips are relatively expensive and require high power consumption. In contrast, previous full software implementations show lower performance even with almost 100% CPU usages, which would disrupt other multi-threaded applications, In this paper, we present a cost-effective way of accelerating both of OpenVG and SVG Tiny, based on the multimedia-processing hardware, which is wide-spread on the media devices and mobile phones. Through the effective use of these multimedia processors, we successfully accelerated OpenVG and SVG Tiny at least 3.5 times to at most 30 times, even with lower power consumption and lower CPU usage.