• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.16 no.2
• /
• pp.273-278
• /
• 2012

In this contribution, we design and implement an SPI hardware interface for the microprocessor to communicate with the MMC (Multi-Media Card) in an embedded system. Proposed architecture is compatible with the APB in AMBA bus architecture. Embedding OS in an embedded system means a big burden in terms of hardware and software ending up with performance decline. In this paper, we adopt the concept of SPI communication without using OS in the embedded system and implement in a form of FPGA chip. The designed SPI module was automatically synthesized, placed, and routed. Implementation was performed through the Altera FPGA and well operated at 25MHz clock frequency, which satisfied our target speed.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.9 no.5
• /
• pp.1111-1116
• /
• 2005

The necessity of the home network have been enlarged gradually according to the distribution of ultra-high speed internet, the expansion of a digital information equipment and the change of a life pattern. In this paper, we proposed the embedded ethernet module that could be operate on eight bit system, but it could control home appliance with full ethernet speed. The embedded ethernet module consists of 8051 MCU and Hardware TCP/IP. In this module, we construct simple web server and port remote control program for I/O device control. We verified through internet that the developed embedded ethernet module could control and check home appliances anywhere and anytime. We expect the developed ethernet module can build up niche market at home network. And it will be helpful to activate home network market.

• Speech Sciences
• /
• v.11 no.2
• /
• pp.181-192
• /
• 2004

This paper presents an efficient speech interactive agent rendering smooth car navigation and Telematics services, by employing embedded automatic speech recognition (ASR), distributed speech recognition (DSR) and text-to-speech (ITS) modules, all while enabling safe driving. A speech interactive agent is essentially a conversational tool providing command and control functions to drivers such' as enabling navigation task, audio/video manipulation, and E-commerce services through natural voice/response interactions between user and interface. While the benefits of automatic speech recognition and speech synthesizer have become well known, involved hardware resources are often limited and internal communication protocols are complex to achieve real time responses. As a result, performance degradation always exists in the embedded H/W system. To implement the speech interactive agent to accommodate the demands of user commands in real time, we propose to optimize the hardware dependent architectural codes for speed-up. In particular, we propose to provide a composite solution through memory reconfiguration and efficient arithmetic operation conversion, as well as invoking an effective out-of-vocabulary rejection algorithm, all made suitable for system operation under limited resources.

• Journal of KIISE:Computer Systems and Theory
• /
• v.33 no.5
• /
• pp.257-266
• /
• 2006

Recently TCP/IP Offload Engine (TOE) technology, which processes TCP/IP on a network adapter instead of the host CPU, has become an important approach to reduce TCP/IP processing overhead in the host CPU. There have been two approaches to implementing TOE: software TOE, in which TCP/IP is processed by an embedded processor on a network adapter; and hardware TOE, in which all TCP/IP functions are implemented by hardware. This paper proposes a hybrid TOE that combines software and hardware functions in the TOE. In the hybrid TOE, functions that cannot have guaranteed performance on an embedded processor because of heavy load are implemented by hardware. Other functions that do not impose as much load are implemented by software on embedded processors. The hybrid TOE guarantees network performance near that of hardware TOE and it has the advantage of flexibility, because it is easy to add new functions or offload upper-level protocols of TCP/IP. In this paper, we developed a prototype board with an FPGA and an ARM processor to implement a hybrid TOE prototype. We implemented the hardware modules on the FPGA and the software modules on the ARM processor. We also developed a coprocessing mechanism between the hardware and software modules. Experimental results proved that the hybrid TOE prototype can greatly reduce the load on a host CPU and we analyzed the effects of the coprocessing mechanism. Finally, we analyzed important features that are required to implement a complete hybrid TOE and we predict its performance.

• Journal of Korea Multimedia Society
• /
• v.12 no.2
• /
• pp.200-208
• /
• 2009

JBIG2, as the next generation standard for binary image compression, must be designed in hardware modules for the JBIG2 FAX to be implemented in an embedded equipment. This paper proposes a hardware module of the high-speed Huffman coder for JBIG2. The Huffman coder of JBIG2 uses selectively 15 Huffman tables. As the Huffman coder is designed to use minimal data and have an efficient memory usage, high speed processing is possible. The designed Huffman coder is ported to Virtex-4 FPGA and co-operating with a software modules on the embedded development board using Microblaze core. The designed IP was successfully verified using the simulation function test and hardware-software co-operating test. Experimental results shows the processing time is 10 times faster than that of software only on embedded system, because of hardware design using an efficient memory usage.

• IEMEK Journal of Embedded Systems and Applications
• /
• v.7 no.1
• /
• pp.17-24
• /
• 2012

Recently automotive software has been more complex and needs to be reduced its development time. Software testing of its functionalities and performance should be conducted in an early development phase to reduce time to market and the development cost. Software functional testing can be performed through simulating the hardware, but it is not guaranteed that evaluation of real-time performance using simulation has enough accuracy. Real-time performance can be precisely evaluated with hardware-in-the-loop simulation, but it costs time and effort to set up hardware for testing. In this paper, we suggest a testing system that can evaluate functional requirements and real time properties with a general-purpose development board in the early development phase. In addition, we improve reusability of the testing system through modularized and layered architecture. With the proposed testing system we can contribute to building reliable testing system at low cost without difficulty.

• Proceedings of the IEEK Conference
• /
• 2006.06a
• /
• pp.781-782
• /
• 2006

This treatise proposed environment for Embedded system's development. Virtual platform can help to solve problem that hardware designer can experience at design process of hardware. Compose circuit of most suitable that is verified before mix parts by various kinds method and compose circuit by board level because can do simulation with software and software that is optimized to hardware and offer flexibility that can test. Therefore, can shorten expense that is cost in development and time. Embody development platform for 8051 systems for verification of development platform, and compose and verified system in various kinds structure.

• Journal of Information Processing Systems
• /
• v.17 no.2
• /
• pp.227-241
• /
• 2021

Object detection techniques based on deep learning such as YOLO have high detection performance and precision in a single channel video stream. In order to expand to multiple channel object detection in real-time, however, high-performance hardware is required. In this paper, we propose a novel back-end server framework, a real-time AI vision platform (RAVIP), which can extend the object detection function from single channel to simultaneous multi-channels, which can work well even in low-end server hardware. RAVIP assembles appropriate component modules from the RODEM (real-time object detection module) Base to create per-channel instances for each channel, enabling efficient parallelization of object detection instances on limited hardware resources through continuous monitoring with respect to resource utilization. Through practical experiments, RAVIP shows that it is possible to optimize CPU, GPU, and memory utilization while performing object detection service in a multi-channel situation. In addition, it has been proven that RAVIP can provide object detection services with 25 FPS for all 16 channels at the same time.

• IEMEK Journal of Embedded Systems and Applications
• /
• v.3 no.4
• /
• pp.251-259
• /
• 2008

This paper presents the hardware design of a 32bit floating point based processor. The processor can perform nonlinear functions such as sinusoidal functions, exponential functions, and other mathematical functions. Using the Taylor series and Newton - Raphson method, nonlinear functions are approximated. The processor is actually embedded on an FPGA chip and tested. The numerical accuracy of the functions is compared with those computed by the MATLAB and confirmed the performance of the processor.

• Proceedings of the IEEK Conference
• /
• 2003.07d
• /
• pp.1601-1604
• /
• 2003

본 논문에서는 PDA. Hand PC(HPC)등과 같은 모바일 단말에 운영체제로써 Embedded Linux를 채택하였을 경우 고려해야 할 Hardware 사양, I/O interrupt latency에 따른 성능. 스케줄링 정책에 따른 성능에 대하여 논한다. 대상 타겟으로 사용한 HPC 의 하드웨어 사양에 설명하고, Embedded Linux와의 연동에 있어서 문제점을 살펴본다. 또한 각종 I/O device들의 Interrupt latency에 따른 성능저하와 스케줄링 정책에 의한 성능저하에 대하여 분석하고. 해결 방안에 대하여 논한다. 마지막으로 실제 예로서 Mobile IPv6 S/W Stack을 이용한 실제 검증을 수행하고 성능 향상 방안을 제시한다.