• International Journal of Aeronautical and Space Sciences
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• v.9 no.2
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• pp.121-128
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• 2008

Modularized GPS software defined radio (SDR) has many advantages of applying and modifying algorithm. Hardware based GPS receiver uses many hardware parts (such as RF front, correlators, CPU and other peripherals) that process tracked signal and navigation data to calculate user position, while SDR uses software modules, which run on general purpose CPU platform or embedded DSP. SDR does not have to change hardware part and is not limited by hardware capability when new processing algorithm is applied. The weakness of SDR is that software correlation takes lots of processing time. However, in these days the evolution of processing power of MPU and DSP leads the competitiveness of SDR against the hardware GPS receiver. This paper shows a study of modulization of GPS software platform and it presents development of the GNSS software platform using MATLAB Simulink™. We focus on post processing SDR platform which is usually adapted in research area. The main functions of SDR are GPS signal acquisition, signal tracking, decoding navigation data and calculating stand alone user position from stored data that was down converted and sampled intermediate frequency (IF) data. Each module of SDR platform is categorized by function for applicability for applying for other frequency and GPS signal easily. The developed software platform is tested using stored data which is down-converted and sampled IF data file. The test results present that the software platform calculates user position properly.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.11C
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• pp.148-156
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• 2001

This paper proposed embedded application-specific microprocessor(YS-RDSP) whose structure has an additional DSP processor on chip. The YS-RDSP can execute maximum four instructions in parallel. To make program size shorter, 16-bit and 32-bit instruction lengths are supported in YS-RDSP. The YS-RDSP provides programmability. controllability, DSP processing ability, and includes eight-kilobyte on-chip ROM and eight-kilobyte RAM. System controller on the chip gives three power-down modes for low-power operation, and SLEEP instruction changes operation statue of CPU core and peripherals. YS-RDSP processor was implemented with Verilog HDL on top-down methodology, and it was improved and verified by cycle-based simulator written in C-language. The verified model was synthesized with 0.7um, 3.3V CMOS standard cell library, and the layout size was 10.7mm78.4mm which was implemented by using automatic P&R software.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.1B
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• pp.78-84
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• 2010

A fixed 900 MHz near field RFID system is developed to provide information; market efficiency, jewelry information and the circulation history information in real time, to the customers. The developed RFID system for the jewelry management consists of a reader, antenna and a CPU in a integrated type. The system size is $38\;{\times}\;25\;{\times}\;19\;cm^3$, the operated frequency band of the reader antenna is 905 ~ 926 MHz. The maximum gain of the embedded reader antenna is 5.1 dBii(@ 910 MHz). Honeycomb tag manufactured by RSI Co. is suitable for the jewelry management than another other commercial near field tags. The tagging method and the tagging location of Honeycomb tag are suggested. In the suggested system, the maximum reading range is about 16 cm, and the zone with 100 % recognition rate is 10 cm from the radom of the reader antenna.

• Proceedings of the Korea Contents Association Conference
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• 2008.05a
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• pp.116-120
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• 2008

Smart Camera provides intelligent vision functionalities which can interpret captured video, extract context-aware information and execute a necessary action in real-timeliness in addition to the functionality of network cameras which transmit the compressed acquired videos through networks. Intelligent vision algorithms demand tremendous computations so that real-time processing of computation of intelligent vision algorithms as well as compression and transmission of videos simultaneously is too much burden for a single CPU. Davinci processor of Texas Instruments is a popular ASSP(Application Specific Standard Product) which has dual core architecture of ARM core and DSP core and provides various I/O interfaces as well as networking interface and video acquiring interface necessary for developing digital video embedded applications. In this paper, we report the results of designing and implementing S/W for Davinci-based smart camera. We implement a face detection as an example of vision application and verify the implementation works well. In the future, for the development of a smart camera with more broad and real-time vision functionalities, it is necessary to study about more efficient vision application S/W architecture and optimization of vision algorithms on DSP core of Davichi processor.

• Journal of Satellite, Information and Communications
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• v.9 no.4
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• pp.73-76
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• 2014

With the increasing popularity of multi-core processors, they have been adopted even in embedded systems. Under this circumstance many multimedia applications can be parallelized on multi-core platforms because they usually require heavy computations and extensive memory accesses. This paper proposes an efficient thread-level parallel implementation for color space conversion on multi-core CPU. Thread-level parallelism has been becoming very useful parallel processing paradigm especially on shared memory computing systems. In this work, it is exploited by allocating different input pixels to each thread for concurrent loop executions. For the performance evaluation, this paper evaluate the performace improvements for color conversion on multi-core processors based on the processing speed comparison between its serial implementation and parallel ones. The results shows that thread-level parallel implementations show the overall similar ratios of performance improvements regardless of different multi-cores.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.8
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• pp.1962-1969
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• 2009

During past 20 years we have witnessed brilliant advances in major components of computer system, including CPU, memory, network device and HDD. Among these components, in spite of its tremendous advance in capacity, the HDD is the most performance dragging device until now and there is little affirmative forecasting that this problem will be resolved in the near future. We present a new approach to solve this problem using the NAND Flash memory. Researches utilizing Flash memory as storage medium are abundant these days, but almost all of them are targeted to mobile or embedded devices. Our research aims to develop the NAND Flash memory based storage system enough even for enterprise level server systems. This paper present structural and operational mechanism to overcome the weaknesses of existing NAND Flash memory based storage system, and its evaluation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.4
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• pp.791-799
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• 2008

An image recognition for surrounding conditions is very important in image transmission. In recently rears, as the information infrastructure is more general, the user-centered demands in which they want to identify by object's states image using wire or wireless environment have increased. However, existing mobile solution could be hard to expect high quality mage, because limitation of software processing according as network based on mobile terminal which has low band width supports software codec. To solve this weak point, this paper describes on hardware codec design based on MPEG-4 which is international video compression standard. Implemented system contains the embedded CPU for optimized design and it works high quality service as transmission speed and resolution in mobile circumstance.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.8
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• pp.1511-1518
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• 2007

As studies on ubiquitous computing are actively conducted, desire for various services, including image transmission storage, search and remote monitoring. has been expanding into mobile environment as well as to PCs. while CCTV (closed circuit TV) and un DVR (Digital video Recording) are used in places where security service such as intrusion detection system is required, these are high-end equipment. So it is not easy for ordinary users or household and small-sized companies to use them. Besides, they are difficult to be carried and camera solution for mobile device does not support high-quality function and provides low-definition of QVGA for picture quality. Therefore, in this study, design and implementation of embedded system of high-definition image transmission for ubiquitous mobile device which is not inferior to PC or DVR are described. To this end, usage of dedicated CPU for mobile device and design and implementation of MPEG-4 H/W CODEC also are examined. The implemented system showed excellent performance in mobile environment, in terms of speed, picture quality.

• Journal of IKEEE
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• v.23 no.2
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• pp.388-394
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• 2019

This paper describes a design of security system-on-chip (SoC) that integrates a Cortex-M0 CPU with an AAW (ARIA-AES- Whirlpool) crypto-core which implements two block cipher algorithms of ARIA and AES and a hash function Whirlpool into an unified hardware architecture. The AAW crypto-core was implemented in a small area through hardware sharing based on algorithmic characteristics of ARIA, AES and Whirlpool, and it supports key sizes of 128-bit and 256-bit. The designed security SoC was implemented on FPGA device and verified by hardware-software co-operation. The AAW crypto-core occupied 5,911 slices, and the AHB_Slave including the AAW crypto-core was implemented with 6,366 slices. The maximum clock frequency of the AHB_Slave was estimated at 36 MHz, the estimated throughputs of the ARIA-128 and the AES-128 was 83 Mbps and 78 Mbps respectively, and the throughput of the Whirlpool hash function of 512-bit block was 156 Mbps.

• Journal of IKEEE
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• v.13 no.4
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• pp.116-124
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• 2009

Recently the CPU performance of modem chipsets or multimedia processors of mobile phone is as high as notebook PC. That is why mobile phone has been emerged as a leading ICON on the convergence of consumer electronics. The various applications of mobile phone such as DMB, digital camera, video telephony and internet full browsing are servicing to consumers. To meet all the demands the image quality has been increasingly important. Mobile phone is a portable device which is widely using in both the indoor and outside environments, so it is needed to be overcome to deteriorate image quality depending on environmental light source. Furthermore touch window is popular on the mobile display panel and it makes contrast loss because of low transmittance of ITO film. This paper presents the image enhancement algorithm to be embedded on image enhancement SoC. In contrast enhancement, we propose Clipped histogram stretching method to make it adaptive with the input images, while S-shape curve and gain/offset method for the static application And CIELCh color space is used to sunlight readability enhancement by controlling the lightness and chroma components which is depended on the sensing value of light sensor. Finally the performance of proposed algorithm is evaluated by using histogram, RGB pixel distribution, entropy and dynamic range of resultant images. We expect that the proposed algorithm is suitable for image enhancement of embedded SoC system which is applicable for the small-sized mobile display.