• Journal of the Microelectronics and Packaging Society
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• v.17 no.2
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• pp.11-20
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• 2010

The effects of heat treatment on matte pure tin-plated Cu leadframes at high temperature and humidity conditions were investigated. After 1800 hrs of storage at $55^{\circ}C/85%$ RH, approximately 14.5 ${\mu}m$ long striation-shaped whiskers were observed on the surface of the without postbake treatment (WOPB) samples, while no whiskers were found in with postbake treatment (WPB) samples. The preferred orientations of Sn grains in WOPB and WPB sample did not change after the postbake treatment at $125^{\circ}C$ for 1 hr. However, both changed from (112) to (321) and (101), respectively, after 1800 hrs of storage at $55^{\circ}C/85%$ RH. The tensile stress of 8 MPa generated in as-plated sample was changed to a compression stress of 17 MPa after 2 days in room temperature storage. Due to the grain growth during postbake treatment, the WPB samples have more regular grains than the WOPB samples. In the as-plated sample, 0.32 ${\mu}m$ thickness of planar intermetallic compound (IMC) was observed. The IMCs in the WOPB and WPB samples had two distinct layers with large grains of $Cu_6Sn_5$ and with small grains of ${\eta}-Cu_{6.26}Sn_5$.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.69-74
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• 2013

In this paper, the impact of integrating large number of I/O (Input-Output) and Core power Delivery Network (PDN) on a 6 layers Flip-Chip Ball Grid Array (FCBGA) package is investigated. The impact of core induced supply noise on high-speed I/O interfaces, and high-speed I/O interface's supply noise coupling to adjacent high-speed I/O interfaces' jitter impact are studied. Concurrent stress validation software is used to induce SSO noise on each individual I/O interfaces; and at the same time; periodic noise is introduced from Core PDN into the I/O PDN domain. In order to have the maximum coupling impact, a prototype package is designed to merge the I/O and Core PDN as one while impact on jitter on each I/O interfaces are investigated. In order to understand the impact of the Core to I/O and I/O to I/O noise, the on-die noise measurements were measured and results were compared with the original PDN where each I/O and Core PDN are standalone and isolated are used as a benchmark.

• Journal of the Microelectronics and Packaging Society
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• v.28 no.2
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• pp.1-12
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• 2021

3D printing, which designs product in three dimensions, draws attention as a technology that will lead the future for it dramatically shortens time for production without assembly, no matter how complex the structure is. The paper studies the latest researches of 3D-printed electronics and introduces papers studied electronics components, power supply, circuit interconnection and 3D-printed PCBs' applications. 3D-printed electronics showed possibility to simplify facilities and personalize electric devices by providing one-stop printing process of electronic components, soldering, stacking, and even encapsulation.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.04a
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• pp.43-55
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• 2000

In traditional electronic packages the die and the substrate are interconnected with fine wire. Wire bonding technology is limited to bond pads around the peripheral of the die. As the demand for I/O increases, there will be limitations with wire bonding technology. Flip chip technology eliminates the need for wire bonding by redistributing the bond pads over the entire surface of the die. Instead of wires, the die is attached to the substrate utilizing a direct solder connection. Although several steps and processes are eliminated when utilizing flip chip technology, there are several new problems that must be overcome. The main issue is the mismatch in the coefficient of thermal expansion (CTE) of the silicon die and the substrate. This mismatch will cause premature solder Joint failure. This issue can be compensated for by the use of an underfill material between the die and the substrate. Underfill helps to extend the working life of the device by providing environmental protection and structural integrity. Flux residues may interfere with the flow of underfill encapsulants causing gross solder voids and premature failure of the solder connection. Furthermore, flux residues may chemically react with the underfill polymer causing a change in its mechanical and thermal properties. As flip chip packages decrease in size, cleaning becomes more challenging. While package size continues to decrease, the total number of 1/0 continue to increase. As the I/O increases, the array density of the package increases and as the array density increases, the pitch decreases. If the pitch is decreasing, the standoff is also decreasing. This paper will present the keys to successful flip chip cleaning processes. Process parameters such as time, temperature, solvency, and impingement energy required for successful cleaning will be addressed. Flip chip packages will be cleaned and subjected to JEDEC level 3 testing, followed by accelerated stress testing. The devices will then be analyzed using acoustic microscopy and the results and conclusions reported.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.28 no.9
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• pp.1408-1414
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• 2004

The use of flip-chip technology has many advantages over other approaches for high-density electronic packaging. ACF (anisotropic conductive film) is one of the major flip-chip technologies, which has short chip-to-chip interconnection length, high productivity, and miniaturization of package. In this study, thermal fatigue lift of ACF bonding flip-chip package has been predicted. Elastic and thermal properties of ACF were measured by using DMA and TMA. Temperature dependent nonlinear hi-thermal analysis was conducted and the result was compared with Moire interferometer experiment. Calculated displacement field was well matched with experimental result. Thermal fatigue analysis was also conducted. The maximum shear strain occurs at the outmost located bump. Shear stress-strain curve was obtained to calculate fatigue life. Fatigue model for electronic adhesives was used to predict thermal fatigue life of ACF bonding flip-chip packaging. DOE (Design of Experiment) technique was used to find important design factors. The results show that PCB CTE (Coefficient of Thermal Expansion) and elastic modulus of ACF material are important material parameters. And as important design parameters, chip width, bump pitch and bump width were chose. 2$^{nd}$ DOE was conducted to obtain RSM equation far the choose 3 design parameter. The coefficient of determination ($R^2$) for the calculated RSM equation is 0.99934. Optimum design is conducted using the RSM equation. MMFD (Modified Method for feasible Direction) algorithm is used to optimum design. The optimum value for chip width, bump pitch and bump width were 7.87mm, 430$\mu$m, and 78$\mu$m, respectively. Approximately, 1400 cycles have been expected under optimum conditions. Reliability analysis was conducted to find out guideline for control range of design parameter. Sigma value was calculated with changing standard deviation of design variable. To acquire 6 sigma level thermal fatigue reliability, the Std. Deviation of design parameter should be controlled within 3% of average value.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 1999.08a
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• pp.10-21
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• 1999

Recent progress in manufacture of hot and cold rolled steel strip products and their applications were reviewed. The main trend in the technological development has been to meet the customers' requests for quality improvement and cost reduction. The weight reduction to reduce the fuel consumption is the main issue in the automotive industry and, therefore, various steels have been developed to improve formability as well as strength. The steels include super-EDDQ steels, bainitic steels, TRIP steels, etc. In the oil industry, efforts have been focused to improve strength together with either low temperature toughness or HIC/SSCC resistance. The packaging industry is also a highly competitive market, and steel and canmaking companies have worked cooperatively to develop cost-effective canmaking processes as well as high performance steels. This type of cooperation has also been found important in other industries such as the appliance and electronic industries for the benefits of both steelmakers and customers.

• Electronics and Telecommunications Trends
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• v.33 no.6
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• pp.50-57
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• 2018

As devices have evolved, traditional flip chip bonding and recently commercialized thermocompression bonding techniques have been limited. Laser-assisted bonding is attracting attention as a technology that satisfies both the requirements of mass production and the yield enhancement of advanced packaging interconnections, which are weak points of these bonding technologies. The laser-assisted bonding technique can be applied not only to a two-dimensional bonding but also to a three-dimensional stacked structure, and can be applied to various types of device bonding such as electronic devices; display devices, e.g., LEDs; and sensors.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.4
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• pp.1-10
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• 2020

This paper reviews the recent development of electronic textile technology, mainly focusing on chip-textile bonding. Before the chip-textile bonding, a circuit on the textile should be prepared to supply the electrical power and signal to the chip mounted on the fabrics. Either embroidery with conductive yarn or screen-printing with the conductive paste can be applied to implement the circuit on the fabrics depending on the circuit density and resolution. Next, chip-textile bonding can be performed. There are two choices for chip-textile bonding: fixed connection methods such as soldering, ACF/NCA, embroidery, crimping, and secondly removable connection methods like a hook, magnet, zipper. Following the chip-textile bonding process, the chip on the textile is generally encapsulated using PDMS to ensure reliability like water-proof.

• Journal of Powder Materials
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• v.13 no.5 s.58
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• pp.321-326
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• 2006

Electronic packaging involves interconnecting, powering, protecting, and cooling of semiconductor circuits fur the use in a variety of microelectronic applications. For microelectronic circuits, the main type of failure is thermal fatigue, owing to the different thermal expansion coefficients of semiconductor chips and packaging materials. Therefore, the search for matched coefficients of thermal expansion (CTE) of packaging materials in combination with a high thermal conductivity is the main task for developments of heat sink materials electronics, and good mechanical properties are also required. The aim of this work is to develop copper matrix composites reinforced with carbon nanofibers. The advantages of carbon nanofibers, especially the good thermal conductivity, are utlized to obtain a composite material having a thermal conductivity higher than 400 W/mK. The main challenge is to obtain a homogeneous dispersion of carbon nanofibers in copper. In this paper, a technology for obtaining a homogeneous mixture of copper and nanofibers will be presented and the microstructure and properties of consolidated samples will be discussed. In order to improve the bonding strength between copper and nanofibers, different alloying elements were added. The microstructure and the properties will be presented and the influence of interface modification will be discussed.

• Journal of the Microelectronics and Packaging Society
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• v.14 no.2 s.43
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• pp.23-33
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• 2007

The growing environmental regulation governs the use of lead by RoHS, WEEE, and then. The electronic industry is moving to replace Pb-bearing solder with Pb-free solder. To use the Pb-free solder, microelectronic industry needs consequently the new reliability appraisal such as the packaging for high temperature process, various mechanical change caused by new solder, and the development of Pb-free sloder for long life of product. The evaluation of solder bar and mechanical properties of joint were performed compared with international standard, and new appraisal standard was established. The solderability and spread ability of Sn-0.7Cu solder material showed up to the standard. Shear test of solder joint using by the solder resulted that the shear strengths after thermal shock or after aging were not much lower than the shear strength of as-soldered and that they were also up to the standard.