• Title/Summary/Keyword: Electronic packaging technology

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Flip Chip Process on CNT-Ag Composite Pads for Stretchable Electronic Packaging (신축성 전자패키징을 위한 CNT-Ag 복합패드에서의 플립칩 공정)

  • Choi, Jung Yeol;Oh, Tae Sung
    • Journal of the Microelectronics and Packaging Society
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    • v.20 no.4
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    • pp.17-23
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    • 2013
  • As a basic research to develop stretchable electronic packaging technology, CNT-Ag composite pads were formed on top of Cu/Sn chip bumps and flip-chip bonded using anisotropic conductive adhesive. Average contact resistances of the flip-chip joints were measured with respect to bonding pressure and presence of the CNT-Ag composite pads. When Cu/Sn chip bumps with CNT-Ag composite pads were flip-chip bonded to substrate Cu pads at 25MPa or 50 MPa, contact resistance was too high to measure. The specimen processed by flip-chip bonding the Cu/Sn chip bumps with CNT-Ag composite pads to the substrate Cu pads exhibited an average contact resistance of $213m{\Omega}$. On the other hand, the flip-chip specimens processed by bonding Cu/Sn chip bumps without CNT-Ag composite pads to substrate Cu pads at 25MPa, 50MPa, and 100MPa exhibited average contact resistances of $370m{\Omega}$, $372m{\Omega}$, and $112m{\Omega}$, respectively.

Experiments on the Heat Transfer and Pressure Drop Characteristics of a Channel with Pin-Fin Array (핀-휜을 삽입한 채널의 열전달 및 압력강하 특성 실험)

  • 신지영;손영석;김상민;이대영
    • Korean Journal of Air-Conditioning and Refrigeration Engineering
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    • v.16 no.7
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    • pp.623-629
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    • 2004
  • Rapid development of electronic technology requires small size, high density packaging and high power of electronic devices, which result in more heat generation by the electronic system. Present cooling technology may not be adequate for the thermal management in the current state-of-the-art electronic equipment. Forced convective heat transfer in a channel filled with pin-fin array is studied experimentally in this paper as an alternative cool-ing scheme for a high heat-dissipating equipment. Various configurations of the pin-fin array are selected in order to find out the effect of spacing and diameter of the pin-fin on the heat transfer and pressure drop characteristics. In the low porosity region, interfacial heat transfer and pressure drop seem to show different trend compared to the conventional heat transfer process.

Large Area Wafer-Level High-Power Electronic Package Using Temporary Bonding and Debonding with Double-Sided Thermal Release Tape (양면 열박리 테이프 기반 임시 접합 공정을 이용한 대면적 웨이퍼 레벨 고출력 전자패키지)

  • Hwang, Yong-Sik;Kang, Il-Suk;Lee, Ga-Won
    • Journal of Sensor Science and Technology
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    • v.31 no.1
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    • pp.36-40
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    • 2022
  • High-power devices, such as LEDs and radars, inevitably generate a large amount of heat, which is the main cause of shortening lifespan, deterioration in performance, and failure of electronic devices. The embedded IC process can be a solution; however, when applied to large-area substrates (larger than 8 in), there is a limit owing to the difficulty in the process after wafer thinning. In this study, an 8-in wafer-level high-power electronic package based on the embedded IC process was implemented with temporary bonding and debonding technology using double-sided thermal release tape. Good heat-dissipation characteristics were demonstrated both theoretically and experimentally. These findings will advance the commercialization of high-power electronic packaging.

Transient Liquid Phase Diffusion Bonding Technology for Power Semiconductor Packaging (전력반도체 접합용 천이액상확산접합 기술)

  • Lee, Jeong-Hyun;Jung, Do-hyun;Jung, Jae-Pil
    • Journal of the Microelectronics and Packaging Society
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    • v.25 no.4
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    • pp.9-15
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    • 2018
  • This paper shows the principles and characteristics of the transient liquid phase (TLP) bonding technology for power modules packaging. The power module is semiconductor parts that change and manage power entering electronic devices, and demand is increasing due to the advent of the fourth industrial revolution. Higher operation temperatures and increasing current density are important for the performance of power modules. Conventional power modules using Si chip have reached the limit of theoretical performance development. In addition, their efficiency is reduced at high temperature because of the low properties of Si. Therefore, Si is changed to silicon carbide (SiC) and gallium nitride (GaN). Various methods of bonding have been studied, like Ag sintering and Sn-Au solder, to keep up with the development of chips, one of which is TLP bonding. TLP bonding has the advantages in price and junction temperature over other technologies. In this paper, TLP bonding using various materials and methods is introduced. In addition, new TLP technologies that are combined with other technologies such as metal powder mixing and ultrasonic technology are also reviewed.

Effect of Packaging Material and Oxygen Absorbant on Quality Properties of Yukwa (포장재질 및 탈산소재가 유과의 품질특성에 미치는 영향)

  • Lee, Yong-Hwan;Kum, Jun-Seok;Ahn, Yong-Sik;Kim, Woo-Jung
    • Korean Journal of Food Science and Technology
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    • v.33 no.6
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    • pp.728-736
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    • 2001
  • Effects of packaging material and oxygen absorbant on physical and chemical properties of Yukwu were studied during storage to develop packaging conditions. The packaging materials used were PET/EVOH $(16\;{\mu}m)/PL$ : P1 and PET/EVOH $(24\;{\mu}m)/PL$ : P2 with or without oxygen absorbent (E1A : P1 and E2A : P2 for w/ $O_2$, absorbent, E1EA : P1 and E2EA : P2 for w/o $O_2$, absorbent). Color values for Yukwu indicated that L values of E1A, E1EA, E2A and E2EA were decreased during storage while those b values were increased. Hardness and chewiness of Yukwa were generally decreased, however those of E1A and E1EA were rather increased after 6 weeks of storage. Acid value of E2A had maintained less than 2.0 during 12 weeks of storage. E1A, E2A had the below of 20 in peroxide during 12 weeks. Aroma data by using electronic nose showed that there was no difference after 6 week storage time in different packaging materials. Sensory evaluation (Yukwa odor and rancid odor) showed very similar results with electronic nose one. E2A had the highest value of overall acceptability for sensory evaluation. Hardness and cheweness in physical measurement results had the highest correlation with hardness, crispness, overall-acceptability in sensory evaluation results.

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Technical Trend of TSV(Through Silicon Via) Filling for 3D Wafer Electric Packaging (3D 웨이퍼 전자접합을 위한 관통 비아홀의 충전 기술 동향)

  • Ko, Young-Ki;Ko, Yong-Ho;Bang, Jung-Hwan;Lee, Chang-Woo
    • Journal of Welding and Joining
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    • v.32 no.3
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    • pp.19-26
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    • 2014
  • Through Silicon Via (TSV) technology is the shortest interconnection technology which is compared with conventional wire bonding interconnection technology. Recently, this technology has been also noticed for the miniaturization of electronic devices, multi-functional and high performance. The short interconnection length of TSV achieve can implement a high density and power efficiency. Among the TSV technology, TSV filling process is important technology because the cost of TSV technology is depended on the filling process time and reliability. Various filling methods have been developed like as Cu electroplating method, molten solder insert method and Ti/W deposition method. In this paper, various TSV filling methods were introduced and each filling materials were discussed.

Vacuum Packaging of MEMS (Microelectromechanical System) Devices using LTCC (Low Temperature Co-fired Ceramic) Technology (LTCC 기술을 이용한 MEMS 소자 진공 패키징)

  • 전종인;최혜정;김광성;이영범;김무영;임채임;황건탁;문제도;최원재
    • Journal of the Microelectronics and Packaging Society
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    • v.10 no.1
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    • pp.31-38
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    • 2003
  • In the current electronic technology atmosphere, MEMS (Microelectromechanical System) technology is regarded as one of promising device manufacturing technologies to realize market-demanding device properties. In the packaging of MEMS devices, the packaged structure must maintain hermeticity to protect the devices from a hostile atmosphere during their operations. For such MEMS device vacuum packaging, we introduce the LTCC (Low temperature Cofired Ceramic) packaging technology, in which embedded passive components such as resistors, capacitors and inductors can be realized inside the package. The technology has also the advantages of the shortened length of inner and surface traces, reduced signal delay time due to the multilayer structure and cost reduction by more simplified packaging processes owing to the realization of embedded passives which in turn enhances the electrical performance and increases the reliability of the packages. In this paper, the leakage rate of the LTCC package having several interfaces was measured and the possibility of LTCC technology application to MEMS devices vacuum packaging was investigated and it was verified that improved hermetic sealing can be achieved for various model structures having different types of interfaces (leak rate: stacked via; $4.1{\pm}1.11{\times}10^{-12}$/ Torrl/sec, LTCC/AgPd/solder/Cu-tube; $3.4{\pm}0.33{\times}10^{-12}$/ Torrl/sec). In real application of the LTCC technology, the technology can be successfully applied to the vacuum packaging of the Infrared Sensor Array and the images of light-up lamp through the sensor way in LTCC package structure was presented.

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Dielectric Properties of $Ta_2O_5-SiO_2$ Thin Films Deposited at Room Temperature by Continuous Composition Spread (상온에서 연속 조성 확산법에 의해 증착된 $Ta_2O_5-SiO_2$ 유전특성)

  • Kim, Yun-Hoe;Jung, Keun;Yoon, Seok-Jin;Song, Jong-Han;Park, Kyung-Bong;Choi, Ji-Won
    • Journal of the Microelectronics and Packaging Society
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    • v.17 no.2
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    • pp.35-40
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    • 2010
  • The variations of dielectric properties of $Ta_2O_5-SiO_2$ continuous composition spread thin films prepared by off-axis radio-frequency magnetron sputtering were investigated. The dielectric maps of dielectric constant and loss were plotted via 1500 micron-step measuring. The specific points showing superior dielectric properties of high dielectric constant (k~19.5) and loss (tan${\delta}$<0.05) at 1 MHz were found in area of the distance of 16 mm and 22 mm apart from $SiO_2$ side in $75{\times}25mm^2$ sized Pt/Ti/$SiO_2$/Si(100) substrates.