• Title/Summary/Keyword: Electronic devices

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Piezoelectric Properties of $Pb(Ni_{1/3}Nb_{2/3})O_{3}-PbZrO_{3}-PbTiO_{3}$ Ceramics doped with$Y_{2}O_{3}$ and Their Application to Multilayer Piezoelectric Actuators ($Y_{2}O_{3}$가 첨가된 $Pb(Ni_{1/3}Nb_{2/3})O_{3}-PbZrO_{3}-PbTiO_{3}$ 세라믹의 압전특성 및 적층형 압전 Actuator에 관한 연구)

  • Choi, Hae-Yun;Kwon, Jeong-Ho;Lee, Dae-Su;Kim, Il-Won;Song, Jae-Sung;Jeong, Soon-Jong;Lee, Jae-Shin
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2002.11a
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    • pp.317-321
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    • 2002
  • Piezoelectric properties of $(Pb_{1-x}Y_x)[(Ni_{1/3}Nb_{2/3})_{0.15}(Zr_{1/2}Ti_{1/2)})_{0.85}]O_{3}$ (x=0~0.05) ceramics were investigated, The stoichiometric PNN-PZT ceramics required the sintering temperature above $1100^{\circ}C$, but the addition of $Y_{2}O_{3}$ in the PNN-PZT ceramic lowered the sintering temperature down to $1000^{\circ}C$. In case of x=0.005, the electro-mechanical coupling $factor(K_p)$, the piezoelectric $constant(d_{33})$, and the maximum strain ratio of PNN-PZT ceramics sintered at $1000^{\circ}C$ were 53.1%, 395pC/N, and $2200{\times}10^{-6}$ respectively, A 30-layer piezoelectric actuator$(10{\times}10{\times}1.7mm)$ fabricated with the above material showed the maximum strain of $2.09{\mu}m$ under 100V DC bias.

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The Effects of $Y_{2}O_{3}$ and $Ga_{2}O_{3}$ Addtives on the Microstructure and Piezoelectric Properties of PNN-PZ-PT Ceramics (PNN-PZ-PT 세라믹스의 미세구조 및 암전특성에 대한 $Y_{2}O_{3}$$Ga_{2}O_{3}$의 첨가효과)

  • Kwon, Jeong-Ho;Choi, Hae-Yun;Jeong, Yeon-Hak;Kim, Il-Won;Song, Jae-Sung;Jeong, Soon-Jong;Lee, Jae-Shin
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2002.11a
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    • pp.334-337
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    • 2002
  • In this study, the microstructure, dielectric and piezoelectric properties of $0.15Pb(Ni_{1/3}Nb_{2/3})O_3-0.85(PbZr_{0.5}Ti_{0.5})O_3$(0.15PNN-0.85PZT) ceramics having compositions near the morphotropic phase boundary(MPB) was investigated with respect to the variation of $Y_2O_3$ and $Ga_2O_3$ addition amount. The dielectric properties increased and piezoelectric properties decreased with increasing the amount of $Ga_2O_3$. The solubility limit of $Y_2O_3$ is 0.5mol% in this system. The electro-mechanical coupling factor$(K_p)$ and dielectric constant(${\varepsilon}_r$) were 58.6% and 1755 when the amount of $Y_2O_3$ are 0.5mol%.

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Layer Thickness-dependent Electrical and Optical Properties of Bottom- and Top-emission Organic Light-emitting Diodes

  • An, Hui-Chul;Na, Su-Hwan;Joo, Hyun-Woo;Kim, Tae-Wan
    • Transactions on Electrical and Electronic Materials
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    • v.10 no.1
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    • pp.28-30
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    • 2009
  • We have studied organic layer-thickness dependent electrical and optical properties of bottom- and top-emission devices. Bottom-emission device was made in a structure of ITO(170 nm)/TPD(x nm)/$Alq_3$(y nm)/LiF(0.5 nm)/Al(100 nm), and a top-emission device in a structure of glass/Al(100 nm)/TPD(x nm)/$Alq_3$(y nm)/LiF(0.5 nm)/Al(25 nm). A hole-transport layer of TPD (N,N'-diphenyl-N,N'-di(m-tolyl)-benzidine) was thermally deposited in a range of 35 nm and 65 nm, and an emissive layer of $Alq_3$ (tris-(8-hydroxyquinoline) aluminum) was successively deposited in a range of 50 nm and 100 nm. Thickness ratio between the hole-transport layer and the emissive layer was maintained to be 2:3, and a whole layer thickness was made to be in a range of 85 and 165 nm. From the current density-luminance-voltage characteristics of the bottom-emission devices, a proper thickness of the organic layer (55 nm thick TPD and 85 nm thick $Alq_3$ layer) was able to be determined. From the view-angle dependent emission spectrum of the bottom-emission device, the peak wavelength of the spectrum does not shift as the view angle increases. However, for the top-emission device, there is a blue shift in peak wavelength as the view angle increases when the total layer thickness is thicker than 140 nm. This blue shift is thought to be due to a microcavity effect in organic light-emitting diodes.

Color Discrimination Enhancement Gamut Mapping Using Color Distribution Rearrangement (색 분포 재배열을 이용한 색 분별력 향상 색역 사상)

  • Lee, Jae-Min;Kim, Kyeong-Man;Lee, Chae-Soo;Lee, Cheol-Hee;Ha, Yeong-Ho
    • Journal of the Korean Institute of Telematics and Electronics S
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    • v.36S no.10
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    • pp.58-71
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    • 1999
  • When the same image is displayed in many different devices, the reproduced colors are not same due to the differences in the gamut between devices. Therefore, many gamut mapping method were proposed to solve this problem. In this paper, color discrimination enhancement gamut mapping method using color distribution rearrangement is proposed to reduce the unnecessary distortions by compression mapping and to minimize the decrease of color discrimination by clipping method. The proposed method constructs color distribution, the 3-dimension array of input image's colors. if the maximum of color distribution is within the boundary of printer gamut. the colors are mapped to the same colors. Otherwise, out-of-gamut colors are compressed into the printer gamut with minimum distortion. Consequently, the printer output image was highly consistent with the corresponding monitor image and had an enhanced color discrimination in region where high chroma varied linearly.

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SLC Buffer Performance Improvement using Page Overwriting Method in TLC NAND Flash-based Storage Devices (TLC 낸드 플래시기반 저장 장치에서 페이지 중복쓰기 기법을 이용한 SLC 버퍼 성능향상 연구)

  • Won, Samkyu;Chung, Eui-Young
    • Journal of the Institute of Electronics and Information Engineers
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    • v.53 no.1
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    • pp.36-42
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    • 2016
  • In multi-level-cell based storage devices, TLC NAND has been employed solid state drive due to cost effectiveness. Since TLC has slow performance and low endurance compared with MLC, TLC based storage has adopted SLC buffer scheme to improve performance. To improve SLC buffer scheme, this paper proposes page overwriting method in SLC block. This method provides data updates without erase operation within a limited number. When SLC buffer area is filled up, FTL should execute copying valid pages and erasing it. The proposed method reduces erase counts by 50% or more compared with previous SLC buffer scheme. Simulation results show that the proposed SLC buffer overwrite method achieves 2 times write performance improvement.

Three-phase 3-level and 2-level SVPWM Implementation with 100 kHz Switching Frequency using FPGA (FPGA를 이용한 100 kHz 스위칭 주파수의 3상 3-level과 2-level의 SVPWM의 구현)

  • Moon, Kyeong-Rok;Lee, Dong-Myung
    • Journal of IKEEE
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    • v.24 no.1
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    • pp.19-24
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    • 2020
  • This paper presents a 3-level, 2-level SVPWM technique with 100 kHz switching using Verilog HDL, one of the languages of FPGA. In the case of IGBT devices mainly used in inverters, they have a switching frequency around 20kHz. Recent research and development of next-generation power semiconductor devices such as GAN has enabled switching of more than 100kHz, which can miniaturize power converters, and apply various new algorithms due to the injection of harmonics. In the existing system using the IGBT, the control using the DSP is common, but the controller configuration for 100 kHz switching requires the use of FPGA. Therefore, this paper explains the theory and implementation of SVPWM applied to two-level and three-level inverters using FPGAs and verifies the performance through the output waveform. In addition, this paper implements 3-level SVPWM by using only one carrier instead of using two carriers in the conventional method.

A Design Method on Power Sensefet to Protect High Voltage Power Device (고전압 전력소자를 보호하기 위한 센스펫 설계방법)

  • Kyoung, Sin-Su;Seo, Jun-Ho;Kim, Yo-Han;Lee, Jong-Seok;Kang, Ey-Goo;Sung, Man-Young
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.06a
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    • pp.6-7
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    • 2008
  • Current sensing in power semiconductors involves sensing of over-current in order to protect the device from harsh conditions. This technique is one of the most important functions in stabilizing power semiconductor device modules. The sense FET is very efficient method with low power consumption, fast sensing speed and accuracy. In this paper we have analyzed the characteristics of proposed sense FET and optimized its electrical characteristics to apply conventional 450V power MOSFET devices by numerical and simulation analysis. The proposed sense FET has the n-drift doping concentration $1.5\times10^{14}cm^{-3}$, size of $600{\mu}m^2$ with 4.5 $\Omega$, and off-state leakage current below 50 ${\mu}A$. We offer the layout of the proposed sense FET to process actually. The offerd design and optimization methods is meaningful, which the methods can be applied to the power devices having various breakdown voltages for protection.

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Consideration of Optimized Thickness of Dielectric Layers in Miniaturization of Microwave Devices and Application of Aerosol Deposition Method (마이크로파 소자의 소형화에 있어서 유전체 막의 최적화 두께에 대한 고찰 및 Aerosol Deposition Method의 적용)

  • Kim, Yoon-Hyun;Lee, Dae-Seok;Lee, Ji-Won;Choi, Yoon-Seok;Lee, Young-Jin;Nam, Song-Min
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.06a
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    • pp.349-349
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    • 2008
  • 유비쿼터스 시대를 맞이하여 현재의 전자제품은 고주파 환경에서의 소형화된 마이크로파 소자를 요구하고 있다. 현재 구현되고 있는 마이크로파 소자의 형태는 여러 가지 전송선로 중에 하나로서 금속의 그라운드면 위에 유전체 막을 형성하고 그 위에 금속선을 정밀하게 패터닝하여 각 종 소자를 연결하는 microstrip line의 형태가 많이 사용된다. 이러한 microstrip line 형태의 소자를 설계할 시에 소자 자체의 구조나 유전체 막이 그 소자의 성능을 크게 좌우한다. 여기서 유전체 막은 신호선과 그라운드면 간의 전자파를 집중시켜주어 방사손실을 줄여주는 역할을 한다. 유전체 막의 두께는 소자의 전체적인 크기를 결정하는 요인이 된다. 이는 유전체 막의 두께가 감소할 경우 50 $\Omega$ 임피던스 매칭을 위해 막 위에 형성되는 소자들의 선폭도 동시에 줄여야 하므로 소자의 소형화도 가능 하여진다. 하지만 유전체 막의 두께가 감소할 경우 전자파가 유전체 막에 집중되지 못하여 방사손실이 커지게 되고 소자의 성능이 저하된다. 이런 점을 고려할 때 소자의 소형화를 만족시키면서 동시에 소자의 성능을 유지할 수 있는 유전체 막의 최적화 두께에 대한 연구가 필요하다. 볼 연구에서는 유전체 막의 최적화 두께를 제시하기 위해 대표적 마이크로파 소자인 Edge-Coupled Filter에 대하여 3-D Electromagnetic Simulator로 설계하고 유전체 막의 두께와 Filter 성능 간의 관계를 연구하였다. Filter의 성능은 유지하도록 하면서 유전체 막의 두께를 감소시켜 나간 결과, 약 30 ~ 40 ${\mu}m$ 의 최적화 두께를 얻을 수 있었다. 한편 30 ~ 40 ${\mu}m$ 두께의 후막 공정을 고려할 때 기존의 성막공정으로는 성막시간, 공정의 난이도, 공정온도 등의 면에서 난점이 존재하며 이러한 점들을 극복할 수 있는 Aerosol Deposition Method의 적용 가능성에 대해서 연구하였다.

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A Study on The Improvement of Profile Tilting or Bottom Distortion in HARC (높은 A/R의 콘택 산화막 에칭에서 바닥모양 변형 개선에 관한 연구)

  • Hwang, Won-Tae;Kim, Gli-Ho
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.18 no.5
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    • pp.389-395
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    • 2005
  • The etching technology of the high aspect ratio contact(HARC) is necessary at the critical contact processes of semiconductor devices. Etching the $SiO_{2}$ contact hole with the sub-micron design rule in manufacturing VLSI devices, the unexpected phenomenon of 'profile tilting' or 'bottom distortion' is often observed. This makes a short circuit between neighboring contact holes, which causes to drop seriously the device yield. As the aspect ratio of contact holes increases, the high C/F ratio gases, $C_{4}F_{6}$, $C_{4}F_{8}$ and $C_{5}F_{8}$, become widely used in order to minimize the mask layer loss during the etching process. These gases provide abundant fluorocarbon polymer as well as high selectivity to the mask layer, and the polymer with high sticking yield accumulates at the top-wall of the contact hole. During the etch process, many electrons are accumulated around the asymmetric hole mouth to distort the electric field, and this distorts the ion trajectory arriving at the hole bottom. These ions with the distorted trajectory induce the deformation of the hole bottom, which is called 'profile tilting' or 'bottom distortion'. To prevent this phenomenon, three methods are suggested here. 1) Using lower C/F ratio gases, $CF_{4}$ or $C_{3}F_{8}$, the amount of the Polymer at the hole mouth is reduced to minimize the asymmetry of the hole top. 2) The number of the neighboring holes with equal distance is maximized to get the more symmetry of the oxygen distribution around the hole. 3) The dual frequency plasma source is used to release the excessive charge build-up at the hole mouth. From the suggested methods, we have obtained the nearly circular hole bottom, which Implies that the ion trajectory Incident on the hole bottom is symmetry.

Effect of Ambient Gases on the Characteristics of ITO Thin Films for OLEDs

  • Lee, Yu-Lim;Lee, Kyu-Mann
    • Transactions on Electrical and Electronic Materials
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    • v.10 no.6
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    • pp.203-207
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    • 2009
  • We have investigated the effect of ambient gases on the structural, electrical, and optical characteristics of ITO thin films intended for use as anode contacts in OLED (organic light emitting diodes) devices. These ITO thin films are deposited by radio frequency (RF) magnetron sputtering under different ambient gases (Ar, Ar+$O_2$, and Ar+$H_2$) at $300{^{\circ}C}$. In order to investigate the influences of the oxygen and hydrogen, the flow rate of oxygen and hydrogen in argon mixing gas has been changed from 0.5 sccm to 5 sccm and from 0.01 sccm to 0.25 sccm, respectively. The intensity of the (400) peak in the ITO thin films increased with increasing $O_2$, flow rate whilst the (400) peak was nearly invisible in an atmosphere of Ar+$H_2$. The electrical resistivity of the ITO thin films increased with increasing $O_2$ flow rate, whereas the electrical resistivity decreased sharply under an Ar+$H_2$ atmosphere and was nearly similar regardless of the $H_2$ flow rate. The change of electrical resistivity with changes in the ambient gas composition was mainly interpreted in terms of the charge carrier mobility rather than the charge carrier concentration. All the films showed an average transmittance of over 80% in the visible range. The OLED device was fabricated with different ITO substrates made with the configuration of ITO/$\alpha$-NPD/DPVB/$Alq_3$/LiF/Al in order to elucidate the performance of the ITO substrate. Current density and luminance of OLED devices with ITO thin films deposited in Ar+$H_2$ ambient gas is the highest among all the ITO thin films.